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| author | Tom Rini <trini@ti.com> | 2013-08-18 14:14:34 -0400 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-08-18 14:14:34 -0400 |
| commit | e20cc2ca15b5b0644f51b6e58d530d70acd2bc00 (patch) | |
| tree | f85a22536682ef54e77b1ba95cf0b71d00644632 /board/overo/overo.c | |
| parent | f21876174364391757e743cb8673d3fc5fce7ac7 (diff) | |
| parent | 9ed887caecb9ecb0c68773a1870d143b9f28d3da (diff) | |
| download | u-boot-imx-e20cc2ca15b5b0644f51b6e58d530d70acd2bc00.zip u-boot-imx-e20cc2ca15b5b0644f51b6e58d530d70acd2bc00.tar.gz u-boot-imx-e20cc2ca15b5b0644f51b6e58d530d70acd2bc00.tar.bz2 | |
Merge branch 'master' of git://88.191.163.10/u-boot-arm
Fixup an easy conflict over adding the clk_get prototype and USB_OTG
defines for am33xx having moved.
Conflicts:
arch/arm/include/asm/arch-am33xx/hardware.h
Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'board/overo/overo.c')
| -rw-r--r-- | board/overo/overo.c | 22 |
1 files changed, 14 insertions, 8 deletions
diff --git a/board/overo/overo.c b/board/overo/overo.c index a6e2e93..aace42a 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -142,16 +142,22 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break; case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ - timings->mcfg = MICRON_V_MCFG_165(256 << 20); - timings->ctrla = MICRON_V_ACTIMA_165; - timings->ctrlb = MICRON_V_ACTIMB_165; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; break; case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */ - timings->mcfg = HYNIX_V_MCFG_165(256 << 20); - timings->ctrla = HYNIX_V_ACTIMA_165; - timings->ctrlb = HYNIX_V_ACTIMB_165; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = HYNIX_V_MCFG_200(256 << 20); + timings->ctrla = HYNIX_V_ACTIMA_200; + timings->ctrlb = HYNIX_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + break; + case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */ + timings->mcfg = MCFG(512 << 20, 15); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; break; default: timings->mcfg = MICRON_V_MCFG_165(128 << 20); |