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| author | Stefan Roese <sr@denx.de> | 2008-06-03 20:19:08 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-06-03 20:19:08 +0200 |
| commit | 10a3367955bc2033b288915f8f10d0e507fe2fa1 (patch) | |
| tree | c3ac82364df83db5d5cb963c64b863b77a20445c /board/omap730p2/lowlevel_init.S | |
| parent | 97f7d27c8ecf34879d6b747c10fa9a18c02a4cc0 (diff) | |
| parent | 1f1554841a4c8e069d331176f0c3059fb2bb8280 (diff) | |
| download | u-boot-imx-10a3367955bc2033b288915f8f10d0e507fe2fa1.zip u-boot-imx-10a3367955bc2033b288915f8f10d0e507fe2fa1.tar.gz u-boot-imx-10a3367955bc2033b288915f8f10d0e507fe2fa1.tar.bz2 | |
Merge branch 'master' of /home/stefan/git/u-boot/u-boot
Diffstat (limited to 'board/omap730p2/lowlevel_init.S')
| -rw-r--r-- | board/omap730p2/lowlevel_init.S | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/board/omap730p2/lowlevel_init.S b/board/omap730p2/lowlevel_init.S index 9ab71cf..d4e97a5 100644 --- a/board/omap730p2/lowlevel_init.S +++ b/board/omap730p2/lowlevel_init.S @@ -65,7 +65,7 @@ lowlevel_init: str r1, [r0] /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT2) * + * Set up ARM CLM registers (IDLECT2) * *------------------------------------------------------*/ ldr r0, REG_ARM_IDLECT2 ldr r1, VAL_ARM_IDLECT2 @@ -123,7 +123,7 @@ lock_end: /*------------------------------------------------------* * Turn off the watchdog during init... * - *------------------------------------------------------*/ + *------------------------------------------------------*/ ldr r0, REG_WATCHDOG ldr r1, WATCHDOG_VAL1 str r1, [r0] @@ -158,7 +158,7 @@ watch2Wait: /* Compare. */ cmp r0, #0 /* Skip over EMIF-fast initialization if running from SDRAM. */ - bne skip_sdram + bne skip_sdram /* * Delay for SDRAM initialization. @@ -166,7 +166,7 @@ watch2Wait: mov r3, #0x1800 /* value should be checked */ 3: subs r3, r3, #0x1 /* Decrement count */ - bne 3b + bne 3b ldr r0, REG_SDRAM_CONFIG ldr r1, SDRAM_CONFIG_VAL @@ -239,7 +239,7 @@ common_tc: #ifdef CONFIG_P2_OMAP1610 /* inserting additional 2 clock cycle hold time for LAN */ ldr r0, REG_TC_EMIFS_CS1_ADVANCED - ldr r1, VAL_TC_EMIFS_CS1_ADVANCED + ldr r1, VAL_TC_EMIFS_CS1_ADVANCED str r1, [r0] #endif /* Start MPU Timer 1 */ |