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| author | Dirk Behme <dirk.behme@googlemail.com> | 2009-05-31 12:44:42 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2009-06-12 20:39:53 +0200 |
| commit | 9d4fc99dbdbfda1260aad478e83fca7cdf0e1a32 (patch) | |
| tree | 0f11f99f9ff8cc0306926f0a96f3d1f561ce64b6 /board/omap3/overo/overo.h | |
| parent | 3962c4f9fc4482a6547f3c3d3d5e986e625abb8a (diff) | |
| download | u-boot-imx-9d4fc99dbdbfda1260aad478e83fca7cdf0e1a32.zip u-boot-imx-9d4fc99dbdbfda1260aad478e83fca7cdf0e1a32.tar.gz u-boot-imx-9d4fc99dbdbfda1260aad478e83fca7cdf0e1a32.tar.bz2 | |
OMAP3: Fix CKE1 MUX setting to allow self-refresh
The Beagle rev Cx and Overo boards are using both SDRC CSes. The MUX
setting is needed for the second CS clock signal to allow the 2 RAM
parts to be put in self-refresh correctly. This also works on rev B
Beagle boards with 128M of RAM.
From: Steve Sakoman <steve@sakoman.com>
From: Jean Pihet <jpihet@mvista.com>
Signed-off-by: Jean Pihet <jpihet@mvista.com>
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
Diffstat (limited to 'board/omap3/overo/overo.h')
| -rw-r--r-- | board/omap3/overo/overo.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/omap3/overo/overo.h b/board/omap3/overo/overo.h index b595f6a..0b59120 100644 --- a/board/omap3/overo/overo.h +++ b/board/omap3/overo/overo.h @@ -376,6 +376,6 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\ - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/ #endif |