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authorMarek Vasut <marex@denx.de>2014-04-28 03:38:43 +0200
committerStefano Babic <sbabic@denx.de>2014-09-29 09:02:17 +0200
commit1fb065feae451b8f22cb9b8b156508ea541c36d7 (patch)
tree1520f20f36d0538d4b43988856f806c9093c5dbe /board/olimex
parentca11db2603e58cfee8e64931dcc3c87023ecb1cf (diff)
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arm: mxs: olinuxino: Fine-tune DRAM configuration
Add fine-tuning for the DRAM configuration according to the DRAM chip datasheet. THis configuration applies to both Hynix HY5DU12622DTP and Samsung K5H511538J-D43 . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'board/olimex')
-rw-r--r--board/olimex/mx23_olinuxino/mx23_olinuxino.c30
1 files changed, 30 insertions, 0 deletions
diff --git a/board/olimex/mx23_olinuxino/mx23_olinuxino.c b/board/olimex/mx23_olinuxino/mx23_olinuxino.c
index 65cbbf1..313ab20 100644
--- a/board/olimex/mx23_olinuxino/mx23_olinuxino.c
+++ b/board/olimex/mx23_olinuxino/mx23_olinuxino.c
@@ -78,3 +78,33 @@ int board_init(void)
return 0;
}
+
+/* Fine-tune the DRAM configuration. */
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+ /* Enable Auto Precharge. */
+ dram_vals[3] |= 1 << 8;
+ /* Enable Fast Writes. */
+ dram_vals[5] |= 1 << 8;
+ /* tEMRS = 3*tCK */
+ dram_vals[10] &= ~(0x3 << 8);
+ dram_vals[10] |= (0x3 << 8);
+ /* CASLAT = 3*tCK */
+ dram_vals[11] &= ~(0x3 << 0);
+ dram_vals[11] |= (0x3 << 0);
+ /* tCKE = 1*tCK */
+ dram_vals[12] &= ~(0x7 << 0);
+ dram_vals[12] |= (0x1 << 0);
+ /* CASLAT_LIN_GATE = 3*tCK , CASLAT_LIN = 3*tCK, tWTR=2*tCK */
+ dram_vals[13] &= ~((0xf << 16) | (0xf << 24) | (0xf << 0));
+ dram_vals[13] |= (0x6 << 16) | (0x6 << 24) | (0x2 << 0);
+ /* tDAL = 6*tCK */
+ dram_vals[15] &= ~(0xf << 16);
+ dram_vals[15] |= (0x6 << 16);
+ /* tREF = 1040*tCK */
+ dram_vals[26] &= ~0xffff;
+ dram_vals[26] |= 0x0410;
+ /* tRAS_MAX = 9334*tCK */
+ dram_vals[32] &= ~0xffff;
+ dram_vals[32] |= 0x2475;
+}