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author | pekon gupta <pekon@ti.com> | 2014-07-22 16:03:24 +0530 |
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committer | Tom Rini <trini@ti.com> | 2014-08-25 10:48:12 -0400 |
commit | 9352697aa060e9b1b5d891e4490fdfa6f5ba6114 (patch) | |
tree | 3b99b784f58c2f384f4fe18e562b6911d8f130f9 /board/nvidia/seaboard | |
parent | 54a97d2849979acd84a0475486edf0d0c18e47c7 (diff) | |
download | u-boot-imx-9352697aa060e9b1b5d891e4490fdfa6f5ba6114.zip u-boot-imx-9352697aa060e9b1b5d891e4490fdfa6f5ba6114.tar.gz u-boot-imx-9352697aa060e9b1b5d891e4490fdfa6f5ba6114.tar.bz2 |
board/ti/dra7xx: add support for parallel NOR
This patch adds support for parallel NOR device (S29GL512S10) present on J6-EVM.
The Flash device is connected to GPMC controller on chip-select[0] and accessed
as memory-mapped device. It has data-witdh=x16, capacity-64MBytes(512Mbits) and
is CFI compatible.
As multiple devices are share GPMC pins on this board, so following board
settings are required to detect NOR device:
SW5.1 (NAND_BOOTn) = OFF (logic-1)
SW5.2 (NOR_BOOTn) = ON (logic-0) /* Active-low */
SW5.3 (eMMC_BOOTn) = OFF (logic-1)
SW5.4 (QSPI_BOOTn) = OFF (logic-1)
And also set appropriate SYSBOOT configurations:
SW3.1 (SYSBOOT[ 8])= ON (logic-1) /* selects SYS_CLK1 speed */
SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */
SW3.3 (SYSBOOT[10])= ON (logic-1) /* wait-pin monitoring = enabled */
SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Non Muxed */
SW3.5 (SYSBOOT[12])= OFF (logic-0) /* device type: Non Muxed */
SW3.6 (SYSBOOT[13])= ON (logic-1) /* device bus-width: 1(x16) */
SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */
SW3.8 (SYSBOOT[15])= ON (logic-1) /* reserved */
Also, following changes are required to enable NOR Flash support in
dra7xx_evm board profile:
Diffstat (limited to 'board/nvidia/seaboard')
0 files changed, 0 insertions, 0 deletions