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authorTom Warren <twarren@nvidia.com>2012-12-21 15:59:15 -0700
committerTom Warren <twarren@nvidia.com>2013-01-16 13:40:08 -0700
commit083bbbbe771afce5e06793c6c831367b596cf03e (patch)
tree650a4e0c6d9d22c07a64bb88b36e9cee50be91a1 /board/nvidia/dts/tegra30-cardhu.dts
parent619bd99e5c176c736c3d1bb2e565ade38a103228 (diff)
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Tegra30: fdt: Update DT files with I2C info for T30/Cardhu
Note that T30 does not have a separate/different DVC (power I2C) controller like T20 - all 5 I2C controllers are identical, but DVC_I2C is still used to designate the controller intended for power control (PWR_I2C in the schematics). On Cardhu, it's used to access the PMU and EEPROM, as well as the audio codec, temp sensor, and fuel gauge devices from the OS. Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'board/nvidia/dts/tegra30-cardhu.dts')
-rw-r--r--board/nvidia/dts/tegra30-cardhu.dts41
1 files changed, 41 insertions, 0 deletions
diff --git a/board/nvidia/dts/tegra30-cardhu.dts b/board/nvidia/dts/tegra30-cardhu.dts
index 3012534..60b91b4 100644
--- a/board/nvidia/dts/tegra30-cardhu.dts
+++ b/board/nvidia/dts/tegra30-cardhu.dts
@@ -7,8 +7,49 @@
model = "NVIDIA Cardhu";
compatible = "nvidia,cardhu", "nvidia,tegra30";
+ aliases {
+ i2c0 = "/i2c@7000d000";
+ i2c1 = "/i2c@7000c000";
+ i2c2 = "/i2c@7000c400";
+ i2c3 = "/i2c@7000c500";
+ i2c4 = "/i2c@7000c700";
+ };
+
memory {
device_type = "memory";
reg = <0x80000000 0x40000000>;
};
+
+ clocks {
+ clk_32k: clk_32K {
+ clock-frequency = <32768>;
+ };
+ osc {
+ clock-frequency = <12000000>;
+ };
+ };
+
+ clock@60006000 {
+ clocks = <&clk_32k &osc>;
+ };
+
+ i2c@7000c000 {
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000c400 {
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000c500 {
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000c700 {
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000d000 {
+ clock-frequency = <100000>;
+ };
};