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| author | Tom Warren <twarren.nvidia@gmail.com> | 2013-02-08 07:25:31 +0000 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2013-03-14 11:06:41 -0700 |
| commit | b77c3547e867f7876b3f970125c45d556588d9cb (patch) | |
| tree | 1d4bc63e6940d611cd965410f16c6ae0b892f68a /board/nvidia/dts/tegra20-ventana.dts | |
| parent | e32624ef820f821b94333402788e79979681eb29 (diff) | |
| download | u-boot-imx-b77c3547e867f7876b3f970125c45d556588d9cb.zip u-boot-imx-b77c3547e867f7876b3f970125c45d556588d9cb.tar.gz u-boot-imx-b77c3547e867f7876b3f970125c45d556588d9cb.tar.bz2 | |
Tegra114: fdt: Update DT files with I2C info for T114/Dalmore
T114, like T30, does not have a separate/different DVC (power I2C)
controller like T20 - all 5 I2C controllers are identical, but
I2C5 is used to designate the controller intended for power
control (PWR_I2C in the schematics). PWR_I2C is set to 400KHz.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'board/nvidia/dts/tegra20-ventana.dts')
0 files changed, 0 insertions, 0 deletions