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authorStephen Warren <swarren@nvidia.com>2013-06-18 09:46:51 -0600
committerTom Warren <twarren@nvidia.com>2013-07-11 14:15:16 -0700
commitb46694df845d8e2f654a871c24849cc217d4b5d2 (patch)
treeee010aa0a17f2b2f3032f96dd24131c98ec19890 /board/nvidia/dts/tegra20-harmony.dts
parentd6cf707e819546623ed742b2324e8b4f106fcf5d (diff)
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ARM: tegra: enable LCD panel on Harmony
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'board/nvidia/dts/tegra20-harmony.dts')
-rw-r--r--board/nvidia/dts/tegra20-harmony.dts32
1 files changed, 32 insertions, 0 deletions
diff --git a/board/nvidia/dts/tegra20-harmony.dts b/board/nvidia/dts/tegra20-harmony.dts
index 7934e4a..b115f87 100644
--- a/board/nvidia/dts/tegra20-harmony.dts
+++ b/board/nvidia/dts/tegra20-harmony.dts
@@ -17,6 +17,17 @@
reg = <0x00000000 0x40000000>;
};
+ host1x {
+ status = "okay";
+ dc@54200000 {
+ status = "okay";
+ rgb {
+ status = "okay";
+ nvidia,panel = <&lcd_panel>;
+ };
+ };
+ };
+
serial@70006300 {
clock-frequency = < 216000000 >;
};
@@ -70,4 +81,25 @@
power-gpios = <&gpio 70 0>; /* gpio PI6 */
bus-width = <8>;
};
+
+ lcd_panel: panel {
+ clock = <42430000>;
+ xres = <1024>;
+ yres = <600>;
+ left-margin = <138>;
+ right-margin = <34>;
+ hsync-len = <136>;
+ lower-margin = <4>;
+ upper-margin = <21>;
+ vsync-len = <4>;
+ hsync-active-high;
+ vsyncx-active-high;
+ nvidia,bits-per-pixel = <16>;
+ nvidia,pwm = <&pwm 0 0>;
+ nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */
+ nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
+ nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
+ nvidia,panel-vdd-gpios = <&gpio 22 0>; /* PC6 */
+ nvidia,panel-timings = <0 0 200 0 0>;
+ };
};