ARM: tegra: pinmux naming consistency fixes

Clean up the naming of pinmux-related objects:
* Refer to drive groups rather than pad groups to match the Linux kernel.
* Ensure all pinmux API types are prefixed with pmux_, values (defines)
  are prefixed with PMUX_, and functions prefixed with pinmux_.
* Modify a few type names to make their content clearer.
* Minimal changes to SoC-specific .h/.c files are made so the code still
  compiles. A separate per-SoC change will be made immediately following,
  in order to keep individual patch size down.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

2 files changed, 25 insertions, 24 deletions

diff --git a/board/nvidia/dalmore/dalmore.c b/board/nvidia/dalmore/dalmore.c
index 2c23a29..f2d05af 100644
--- a/board/nvidia/dalmore/dalmore.c
+++ b/board/nvidia/dalmore/dalmore.c
@@ -29,17 +29,18 @@
  */
 void pinmux_init(void)
 {
-	pinmux_config_table(tegra114_pinmux_set_nontristate,
+	pinmux_config_pingrp_table(tegra114_pinmux_set_nontristate,
 		ARRAY_SIZE(tegra114_pinmux_set_nontristate));
 
-	pinmux_config_table(tegra114_pinmux_common,
+	pinmux_config_pingrp_table(tegra114_pinmux_common,
 		ARRAY_SIZE(tegra114_pinmux_common));
 
-	pinmux_config_table(unused_pins_lowpower,
+	pinmux_config_pingrp_table(unused_pins_lowpower,
 		ARRAY_SIZE(unused_pins_lowpower));
 
 	/* Initialize any non-default pad configs (APB_MISC_GP regs) */
-	padgrp_config_table(dalmore_padctrl, ARRAY_SIZE(dalmore_padctrl));
+	pinmux_config_drvgrp_table(dalmore_padctrl,
+		ARRAY_SIZE(dalmore_padctrl));
 }
 
 #if defined(CONFIG_TEGRA_MMC)
diff --git a/board/nvidia/dalmore/pinmux-config-dalmore.h b/board/nvidia/dalmore/pinmux-config-dalmore.h
index 9dcd5e4..6069fb6 100644
--- a/board/nvidia/dalmore/pinmux-config-dalmore.h
+++ b/board/nvidia/dalmore/pinmux-config-dalmore.h
@@ -17,9 +17,9 @@
 #ifndef _PINMUX_CONFIG_DALMORE_H_
 #define _PINMUX_CONFIG_DALMORE_H_
 
-#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io)	\
+#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io)		\
 	{							\
-		.pingroup	= PINGRP_##_pingroup,		\
+		.pingrp		= PINGRP_##_pingrp,		\
 		.func		= PMUX_FUNC_##_mux,		\
 		.pull		= PMUX_PULL_##_pull,		\
 		.tristate	= PMUX_TRI_##_tri,		\
@@ -29,9 +29,9 @@
 		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
 	}
 
-#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
+#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od)	\
 	{							\
-		.pingroup	= PINGRP_##_pingroup,		\
+		.pingrp		= PINGRP_##_pingrp,		\
 		.func		= PMUX_FUNC_##_mux,		\
 		.pull		= PMUX_PULL_##_pull,		\
 		.tristate	= PMUX_TRI_##_tri,		\
@@ -41,9 +41,9 @@
 		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
 	}
 
-#define DDC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _rcv_sel) \
+#define DDC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _rcv_sel) \
 	{							\
-		.pingroup	= PINGRP_##_pingroup,		\
+		.pingrp		= PINGRP_##_pingrp,		\
 		.func		= PMUX_FUNC_##_mux,		\
 		.pull		= PMUX_PULL_##_pull,		\
 		.tristate	= PMUX_TRI_##_tri,		\
@@ -53,9 +53,9 @@
 		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
 	}
 
-#define VI_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
+#define VI_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
 	{							\
-		.pingroup	= PINGRP_##_pingroup,		\
+		.pingrp		= PINGRP_##_pingrp,		\
 		.func		= PMUX_FUNC_##_mux,		\
 		.pull		= PMUX_PULL_##_pull,		\
 		.tristate	= PMUX_TRI_##_tri,		\
@@ -65,9 +65,9 @@
 		.ioreset	= PMUX_PIN_IO_RESET_##_ioreset	\
 	}
 
-#define CEC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od)	\
+#define CEC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od)		\
 	{								\
-		.pingroup   = PINGRP_##_pingroup,			\
+		.pingrp     = PINGRP_##_pingrp,				\
 		.func       = PMUX_FUNC_##_mux,				\
 		.pull       = PMUX_PULL_##_pull,			\
 		.tristate   = PMUX_TRI_##_tri,				\
@@ -79,19 +79,19 @@
 
 #define USB_PINMUX CEC_PINMUX
 
-#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
 	{						\
-		.padgrp = PDRIVE_PINGROUP_##_padgrp,	\
+		.drvgrp = PDRIVE_PINGROUP_##_drvgrp,	\
 		.slwf   = _slwf,			\
 		.slwr   = _slwr,			\
 		.drvup  = _drvup,			\
 		.drvdn  = _drvdn,			\
-		.lpmd   = PGRP_LPMD_##_lpmd,		\
-		.schmt  = PGRP_SCHMT_##_schmt,		\
-		.hsm    = PGRP_HSM_##_hsm,		\
+		.lpmd   = PMUX_LPMD_##_lpmd,		\
+		.schmt  = PMUX_SCHMT_##_schmt,		\
+		.hsm    = PMUX_HSM_##_hsm,		\
 	}
 
-static struct pingroup_config tegra114_pinmux_common[] = {
+static struct pmux_pingrp_config tegra114_pinmux_common[] = {
 	/* EXTPERIPH1 pinmux */
 	DEFAULT_PINMUX(CLK1_OUT,      EXTPERIPH1,  NORMAL,    NORMAL,   OUTPUT),
 
@@ -286,13 +286,13 @@ static struct pingroup_config tegra114_pinmux_common[] = {
 	DEFAULT_PINMUX(GPIO_X6_AUD,   SPI6,        UP,        TRISTATE, INPUT),
 };
 
-static struct pingroup_config unused_pins_lowpower[] = {
+static struct pmux_pingrp_config unused_pins_lowpower[] = {
 	DEFAULT_PINMUX(CLK1_REQ,      RSVD3,       DOWN, TRISTATE, OUTPUT),
 	DEFAULT_PINMUX(USB_VBUS_EN1,  RSVD3,       DOWN, TRISTATE, OUTPUT),
 };
 
 /* Initially setting all used GPIO's to non-TRISTATE */
-static struct pingroup_config tegra114_pinmux_set_nontristate[] = {
+static struct pmux_pingrp_config tegra114_pinmux_set_nontristate[] = {
 	DEFAULT_PINMUX(GPIO_X4_AUD,     RSVD1,  DOWN,    NORMAL,    OUTPUT),
 	DEFAULT_PINMUX(GPIO_X5_AUD,     RSVD1,  UP,      NORMAL,    INPUT),
 	DEFAULT_PINMUX(GPIO_X6_AUD,     RSVD3,  UP,      NORMAL,    INPUT),
@@ -362,8 +362,8 @@ static struct pingroup_config tegra114_pinmux_set_nontristate[] = {
 	DEFAULT_PINMUX(SDMMC3_CD_N,     SDMMC3, UP,       NORMAL,   INPUT),
 };
 
-static struct padctrl_config dalmore_padctrl[] = {
-	/* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+static struct pmux_drvgrp_config dalmore_padctrl[] = {
+	/* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
 	DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
 		SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, NONE, NONE),
 };