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| author | Simon Glass <sjg@chromium.org> | 2011-09-21 12:40:05 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-10-27 21:56:29 +0200 |
| commit | c3cf49d247d6749bdb65d9538ecd2738195e6a21 (patch) | |
| tree | 85df919c2faf4991e636d6c6599cdebcf2320a9f /board/nvidia/common | |
| parent | 4ed59e70e4e0309794d532120d8c357b308b0e23 (diff) | |
| download | u-boot-imx-c3cf49d247d6749bdb65d9538ecd2738195e6a21.zip u-boot-imx-c3cf49d247d6749bdb65d9538ecd2738195e6a21.tar.gz u-boot-imx-c3cf49d247d6749bdb65d9538ecd2738195e6a21.tar.bz2 | |
tegra2: Rename PIN_ to PINGRP_
The pin groupings are better named PINGRP, since on Tegra2 they refer to
multiple pins.
Sorry about this, but better to get it right now when there is only a small
amount of code affected.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'board/nvidia/common')
| -rw-r--r-- | board/nvidia/common/board.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 9672c5e..35ff2ef 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -94,15 +94,15 @@ static void pin_mux_uart(void) reg &= 0xFFF0FFFF; /* IRRX_/IRTX_SEL [19:16] = 00 UARTA */ writel(reg, &pmt->pmt_ctl_c); - pinmux_tristate_disable(PIN_IRRX); - pinmux_tristate_disable(PIN_IRTX); + pinmux_tristate_disable(PINGRP_IRRX); + pinmux_tristate_disable(PINGRP_IRTX); #endif /* CONFIG_TEGRA2_ENABLE_UARTA */ #if defined(CONFIG_TEGRA2_ENABLE_UARTD) reg = readl(&pmt->pmt_ctl_b); reg &= 0xFFFFFFF3; /* GMC_SEL [3:2] = 00, UARTD */ writel(reg, &pmt->pmt_ctl_b); - pinmux_tristate_disable(PIN_GMC); + pinmux_tristate_disable(PINGRP_GMC); #endif /* CONFIG_TEGRA2_ENABLE_UARTD */ } @@ -138,9 +138,9 @@ static void pin_mux_mmc(void) reg |= (3 << 0); /* GME_SEL [1:0] = 11 SDIO4 */ writel(reg, &pmt->pmt_ctl_d); - pinmux_tristate_disable(PIN_ATB); - pinmux_tristate_disable(PIN_GMA); - pinmux_tristate_disable(PIN_GME); + pinmux_tristate_disable(PINGRP_ATB); + pinmux_tristate_disable(PINGRP_GMA); + pinmux_tristate_disable(PINGRP_GME); /* SDMMC3 */ /* SDIO3_CLK, SDIO3_CMD, SDIO3_DAT[3:0] */ @@ -151,9 +151,9 @@ static void pin_mux_mmc(void) reg |= (2 << 14); /* SDD_SEL [15:14] = 01 SDIO3 */ writel(reg, &pmt->pmt_ctl_d); - pinmux_tristate_disable(PIN_SDC); - pinmux_tristate_disable(PIN_SDD); - pinmux_tristate_disable(PIN_SDB); + pinmux_tristate_disable(PINGRP_SDC); + pinmux_tristate_disable(PINGRP_SDD); + pinmux_tristate_disable(PINGRP_SDB); } #endif |