Merge branch 'master' of git://git.denx.de/u-boot-arm

* 'master' of git://git.denx.de/u-boot-arm: (145 commits)
  beagleboard: enable HUB power on all variants of the BeagleBoard
  dm3730: enable dpll5
  ehci-hcd: Allow cleanups to happen gracefully on a timeout.
  OMAP3: Add DSS driver for OMAP3
  led: Remove state-saving of led for toggle functionality and add toggle option to led command
  led: Fixed setting of STATUS_LED_BIT1 when led_name is 'all'
  led: correct off/on locations in structure
  led: added cmd_led to Makefile
  BeagleBoard: fix LED 0/1 in driver
  Corrected LED name match finding avoiding extraneous Usage printouts
  BeagleBoard: config: updated default configuration
  BeagleBoard: config: Enabled multibus support for I2C in configuration
  BeagleBoard: config: add optargs/buddy/camera
  BeagleBoard: config: increase command-line functionality
  BeagleBoard: config: make mtest run
  BeagleBoard: config: enable DSS
  BeagleBoard: config: enable asix driver and dhcp
  BeagleBoard: config: enable networking
  BeagleBoard: config: decrease bootdelay to 2 seconds
  BeagleBoard: config: use uImage.beagle for tftp
  BeagleBoard: config: hardcode MAC for onboard SMSC
  BeagleBoard: config: load kernel from MMC ext, not FAT
  BeagleBoard: Configure DVI/S-video
  BeagleBoard: Added userbutton command
  BeagleBoard: turn off clocks in ehci_stop
  USB: Remove __attribute__ ((packed)) for struct ehci_hccr and ehci_hcor
  beagleboard: add support for xM revision C
  beagle: pass expansionboard name in bootargs
  OMAP: Remove omapfb.debug=y from Beagle and Overo env settings
  OMAP3 Beagle Pin Mux initialization glitch fix
  da850: modifications for Logic PD Rev.3 AM18xx EVM
  da850: fix the channel number for EMAC teardown init
  da850: add support for Spectrum Digital AM18xx EVM
  da850: add support to wake up DSP during board init
  da850: modify the U-Boot prompt string
  da850: add NOR boot mode support
  da8xx: add support for multiple PLL controllers
  da850: indicate cache usage disable in config file
  dm365: modify boot prompt from dm365 to dm36x
  dm365: disable cache usage due to coherency issues
  dm6446: disable cache usage due to coherency issues
  OMAP3: Remove legacy mmc driver
  devkit8000: Use generic MMC driver
  TI OMAP3 SDP3430: Use generic MMC driver
  AM3517 CraneBoard: Use generic MMC driver
  OMAP3: pandora: Use generic MMC driver
  OMAP3: Zoom2: Use generic MMC driver
  OMAP3: Zoom1: Use generic MMC driver
  OMAP3: DIG297: Use generic MMC driver
  OMAP3: CM-T35: Use generic MMC driver
  am3517evm: Use generic MMC driver
  omap3evm: Use generic MMC driver
  omap3:clock: check cpu_family before enabling clks for IVA & CAM
  omap3:clock: configure GFX clock to 200MHz for AM/DM37x
  OMAP3/4: Increase console I/O buffer size
  PXA: vpac270: Remove re-defined CONFIG_SYS_TEXT_BASE
  PXA: Fix CSB226, fix monitor length
  PXA: Fix Lubbock, remove redundant parenthesis
  armv7: cache: remove flush on un-aligned invalidate
  armv7: stronger barrier for cache-maintenance operations
  omap: enable caches at system start-up
  arm: do not force d-cache enable on all boards
  ORIGEN: Add MMC SPL support
  ARMV7: Add support for Samsung ORIGEN board
  i2c:gpio:s5p: Enable I2C GPIO on the GONI target
  i2c:gpio:s5p: I2C GPIO Software implementation (via soft_i2c)
  Tegra2: Use clock and pinmux functions to simplify code
  Tegra2: Add additional pin multiplexing features
  Tegra2: Add more clock support
  Tegra2: Add microsecond timer function
  ARM: remove broken "at91rm9200dk" board
  ARM: remove broken "m501sk" board
  ARM: remove broken "kb9202" board
  ARM: remove broken "csb637" board
  ARM: remove broken "cmc_pu2" board
  ARM: remove broken "at91cap9adk" board
  ARM: remove broken "voiceblue" board
  ARM: remove broken "smdk2400" board
  ARM: remove broken "sbc2410x" board
  ARM: remove broken "netstar" board
  ARM: remove broken "mx1fs2" board
  ARM: remove broken "lpd7a40x" boards
  ARM: remove broken "edb93xx" boards
  ARM: remove broken "B2" board
  ARM: remove broken "armadillo" board
  ARM: remove broken "assabet" board
  ARM: versatile: drop warnings
  IMX: scb9328: drop warnings
  MX31: imx31_litekit: make use of GPIO framework
  MX31: mx31ads: make use of GPIO framework
  MX5: mx51evk: make use of GPIO framework
  MX35: mx35pdk: make use of GPIO framework
  MX5: mx53loco: make use of GPIO framework
  MX5: mx53evk: make use of GPIO framework
  MX5: vision2: make use of GPIO framework
  MX5: mx53smd: make use of GPIO framework
  MX5: mx53ard: make use of GPIO framework
  MX25: zmx25: make use of GPIO framework
  MX5: efikamx: make use of GPIO framework
  MX31: QONG: make use of GPIO framework
  MX35: make use of GPIO framework for MX35 processor
  MX5: make use of GPIO framework for MX5 processor
  MX31: make use of GPIO framework for MX31 processor
  MX25: make use of GPIO framework for MX25 processor
  IMX: uniform GPIO interface using GPIO framework
  MX: MX35 / MX5: uniform clock command with powerpc
  MX35: MX35PDK: support additional RAM on CSD1
  mx53: ddr3: Update DD3 initialization
  ARM: MX51: PLL errata workaround
  ARM: versatilepb : drop warnings due to double definitions
  omap4: increase SRAM budget to fix build error
  omap4: fix build warning due to signed unsigned comparison
  mkimage: Fix 'Unknown OMAP image type - 5'
  omap: fix gpio related build breaks
  gpio:samsung: s5p_ suffix add for GPIO functions (C210_universal)
  SMDKV310: MMC SPL: Remove unwanted dummy functions
  SMDKV310: Fix undefined reference error
  SMDKV310: Fix build error for smdkv310 board
  gpio:samsung s5p_ suffix add for GPIO functions
  mmc: S5P: Support DMA restarts at buffer boundaries
  SMDKV310: Fix host compilation of mkv310_image
  arm: fix bd pointer dereference prior initialization
  arm, lib/board.c: use gd->ram_size instead of bd->bi_memsize
  mx5: Remove CONFIG_L2_OFF and CONFIG_SYS_L2CACHE_OFF
  MX31: removed warnings due to clock.h
  integrator: convert to new build system
  integratorcp: make the board compile
  integratorap: remove hardcoded 32MB memory cmdline
  ...

1 files changed, 35 insertions, 84 deletions

diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 8ab9440..160dac8 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -28,6 +28,7 @@
 #include <asm/arch/sys_proto.h>
 
 #include <asm/arch/clk_rst.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/uart.h>
 #include "board.h"
@@ -76,33 +77,28 @@ int timer_init(void)
 static void clock_init_uart(void)
 {
 	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	struct clk_pll *pll = &clkrst->crc_pll[CLOCK_PLL_ID_PERIPH];
 	u32 reg;
 
-	reg = readl(&clkrst->crc_pllp_base);
-	if (!(reg & PLL_BASE_OVRRIDE)) {
+	reg = readl(&pll->pll_base);
+	if (!(reg & PLL_BASE_OVRRIDE_MASK)) {
 		/* Override pllp setup for 216MHz operation. */
-		reg = (PLL_BYPASS | PLL_BASE_OVRRIDE | PLL_DIVP);
-		reg |= (((NVRM_PLLP_FIXED_FREQ_KHZ/500) << 8) | PLL_DIVM);
-		writel(reg, &clkrst->crc_pllp_base);
+		reg = PLL_BYPASS_MASK | PLL_BASE_OVRRIDE_MASK |
+			(1 << PLL_DIVP_SHIFT) | (0xc << PLL_DIVM_SHIFT);
+		reg |= (NVRM_PLLP_FIXED_FREQ_KHZ / 500) << PLL_DIVN_SHIFT;
+		writel(reg, &pll->pll_base);
 
-		reg |= PLL_ENABLE;
-		writel(reg, &clkrst->crc_pllp_base);
+		reg |= PLL_ENABLE_MASK;
+		writel(reg, &pll->pll_base);
 
-		reg &= ~PLL_BYPASS;
-		writel(reg, &clkrst->crc_pllp_base);
+		reg &= ~PLL_BYPASS_MASK;
+		writel(reg, &pll->pll_base);
 	}
 
-	/* Now do the UART reset/clock enable */
 #if defined(CONFIG_TEGRA2_ENABLE_UARTA)
-	/* Assert Reset to UART */
-	reg = readl(&clkrst->crc_rst_dev_l);
-	reg |= SWR_UARTA_RST;		/* SWR_UARTA_RST = 1 */
-	writel(reg, &clkrst->crc_rst_dev_l);
-
-	/* Enable clk to UART */
-	reg = readl(&clkrst->crc_clk_out_enb_l);
-	reg |= CLK_ENB_UARTA;		/* CLK_ENB_UARTA = 1 */
-	writel(reg, &clkrst->crc_clk_out_enb_l);
+	/* Assert UART reset and enable clock */
+	reset_set_enable(PERIPH_ID_UART1, 1);
+	clock_enable(PERIPH_ID_UART1);
 
 	/* Enable pllp_out0 to UART */
 	reg = readl(&clkrst->crc_clk_src_uarta);
@@ -113,20 +109,12 @@ static void clock_init_uart(void)
 	udelay(2);
 
 	/* De-assert reset to UART */
-	reg = readl(&clkrst->crc_rst_dev_l);
-	reg &= ~SWR_UARTA_RST;		/* SWR_UARTA_RST = 0 */
-	writel(reg, &clkrst->crc_rst_dev_l);
+	reset_set_enable(PERIPH_ID_UART1, 0);
 #endif	/* CONFIG_TEGRA2_ENABLE_UARTA */
 #if defined(CONFIG_TEGRA2_ENABLE_UARTD)
-	/* Assert Reset to UART */
-	reg = readl(&clkrst->crc_rst_dev_u);
-	reg |= SWR_UARTD_RST;		/* SWR_UARTD_RST = 1 */
-	writel(reg, &clkrst->crc_rst_dev_u);
-
-	/* Enable clk to UART */
-	reg = readl(&clkrst->crc_clk_out_enb_u);
-	reg |= CLK_ENB_UARTD;		/* CLK_ENB_UARTD = 1 */
-	writel(reg, &clkrst->crc_clk_out_enb_u);
+	/* Assert UART reset and enable clock */
+	reset_set_enable(PERIPH_ID_UART4, 1);
+	clock_enable(PERIPH_ID_UART4);
 
 	/* Enable pllp_out0 to UART */
 	reg = readl(&clkrst->crc_clk_src_uartd);
@@ -137,9 +125,7 @@ static void clock_init_uart(void)
 	udelay(2);
 
 	/* De-assert reset to UART */
-	reg = readl(&clkrst->crc_rst_dev_u);
-	reg &= ~SWR_UARTD_RST;		/* SWR_UARTD_RST = 0 */
-	writel(reg, &clkrst->crc_rst_dev_u);
+	reset_set_enable(PERIPH_ID_UART4, 0);
 #endif	/* CONFIG_TEGRA2_ENABLE_UARTD */
 }
 
@@ -157,19 +143,15 @@ static void pin_mux_uart(void)
 	reg &= 0xFFF0FFFF;	/* IRRX_/IRTX_SEL [19:16] = 00 UARTA */
 	writel(reg, &pmt->pmt_ctl_c);
 
-	reg = readl(&pmt->pmt_tri_a);
-	reg &= ~Z_IRRX;		/* Z_IRRX = normal (0) */
-	reg &= ~Z_IRTX;		/* Z_IRTX = normal (0) */
-	writel(reg, &pmt->pmt_tri_a);
+	pinmux_tristate_disable(PIN_IRRX);
+	pinmux_tristate_disable(PIN_IRTX);
 #endif	/* CONFIG_TEGRA2_ENABLE_UARTA */
 #if defined(CONFIG_TEGRA2_ENABLE_UARTD)
 	reg = readl(&pmt->pmt_ctl_b);
 	reg &= 0xFFFFFFF3;	/* GMC_SEL [3:2] = 00, UARTD */
 	writel(reg, &pmt->pmt_ctl_b);
 
-	reg = readl(&pmt->pmt_tri_a);
-	reg &= ~Z_GMC;		/* Z_GMC = normal (0) */
-	writel(reg, &pmt->pmt_tri_a);
+	pinmux_tristate_disable(PIN_GMC);
 #endif	/* CONFIG_TEGRA2_ENABLE_UARTD */
 }
 
@@ -183,16 +165,8 @@ static void clock_init_mmc(void)
 	u32 reg;
 
 	/* Do the SDMMC resets/clock enables */
-
-	/* Assert Reset to SDMMC4 */
-	reg = readl(&clkrst->crc_rst_dev_l);
-	reg |= SWR_SDMMC4_RST;		/* SWR_SDMMC4_RST = 1 */
-	writel(reg, &clkrst->crc_rst_dev_l);
-
-	/* Enable clk to SDMMC4 */
-	reg = readl(&clkrst->crc_clk_out_enb_l);
-	reg |= CLK_ENB_SDMMC4;		/* CLK_ENB_SDMMC4 = 1 */
-	writel(reg, &clkrst->crc_clk_out_enb_l);
+	reset_set_enable(PERIPH_ID_SDMMC4, 1);
+	clock_enable(PERIPH_ID_SDMMC4);
 
 	/* Enable pllp_out0 to SDMMC4 */
 	reg = readl(&clkrst->crc_clk_src_sdmmc4);
@@ -206,20 +180,10 @@ static void clock_init_mmc(void)
 	 */
 	udelay(2);
 
-	/* De-assert reset to SDMMC4 */
-	reg = readl(&clkrst->crc_rst_dev_l);
-	reg &= ~SWR_SDMMC4_RST;		/* SWR_SDMMC4_RST = 0 */
-	writel(reg, &clkrst->crc_rst_dev_l);
-
-	/* Assert Reset to SDMMC3 */
-	reg = readl(&clkrst->crc_rst_dev_u);
-	reg |= SWR_SDMMC3_RST;		/* SWR_SDMMC3_RST = 1 */
-	writel(reg, &clkrst->crc_rst_dev_u);
+	reset_set_enable(PERIPH_ID_SDMMC4, 1);
 
-	/* Enable clk to SDMMC3 */
-	reg = readl(&clkrst->crc_clk_out_enb_u);
-	reg |= CLK_ENB_SDMMC3;		/* CLK_ENB_SDMMC3 = 1 */
-	writel(reg, &clkrst->crc_clk_out_enb_u);
+	reset_set_enable(PERIPH_ID_SDMMC3, 1);
+	clock_enable(PERIPH_ID_SDMMC3);
 
 	/* Enable pllp_out0 to SDMMC4, set divisor to 11 for 20MHz */
 	reg = readl(&clkrst->crc_clk_src_sdmmc3);
@@ -230,10 +194,7 @@ static void clock_init_mmc(void)
 	/* wait for 2us */
 	udelay(2);
 
-	/* De-assert reset to SDMMC3 */
-	reg = readl(&clkrst->crc_rst_dev_u);
-	reg &= ~SWR_SDMMC3_RST;		/* SWR_SDMMC3_RST = 0 */
-	writel(reg, &clkrst->crc_rst_dev_u);
+	reset_set_enable(PERIPH_ID_SDMMC3, 0);
 }
 
 /*
@@ -257,13 +218,9 @@ static void pin_mux_mmc(void)
 	reg |= (3 << 0);	/* GME_SEL [1:0] = 11 SDIO4 */
 	writel(reg, &pmt->pmt_ctl_d);
 
-	reg = readl(&pmt->pmt_tri_a);
-	reg &= ~Z_ATB;		/* Z_ATB = normal (0) */
-	reg &= ~Z_GMA;		/* Z_GMA = normal (0) */
-	writel(reg, &pmt->pmt_tri_a);
-	reg = readl(&pmt->pmt_tri_b);
-	reg &= ~Z_GME;		/* Z_GME = normal (0) */
-	writel(reg, &pmt->pmt_tri_b);
+	pinmux_tristate_disable(PIN_ATB);
+	pinmux_tristate_disable(PIN_GMA);
+	pinmux_tristate_disable(PIN_GME);
 
 	/* SDMMC3 */
 	/* SDIO3_CLK, SDIO3_CMD, SDIO3_DAT[3:0] */
@@ -274,13 +231,9 @@ static void pin_mux_mmc(void)
 	reg |= (2 << 14);	/* SDD_SEL [15:14] = 01 SDIO3 */
 	writel(reg, &pmt->pmt_ctl_d);
 
-	reg = readl(&pmt->pmt_tri_b);
-	reg &= ~Z_SDC;		/* Z_SDC = normal (0) */
-	reg &= ~Z_SDD;		/* Z_SDD = normal (0) */
-	writel(reg, &pmt->pmt_tri_b);
-	reg = readl(&pmt->pmt_tri_d);
-	reg &= ~Z_SDB;		/* Z_SDB = normal (0) */
-	writel(reg, &pmt->pmt_tri_d);
+	pinmux_tristate_disable(PIN_SDC);
+	pinmux_tristate_disable(PIN_SDD);
+	pinmux_tristate_disable(PIN_SDB);
 }
 
 /*
@@ -318,8 +271,6 @@ int board_init(void)
 {
 	/* boot param addr */
 	gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
-	/* board id for Linux */
-	gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
 
 	return 0;
 }