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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2013-12-10 15:02:23 +0530 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-12-18 21:14:45 -0500 |
| commit | b5e01eecc89e3e5c2ed3c17b803529be3c3702fb (patch) | |
| tree | 73824a5325ebcf7c0c7cfe28ac5790655f7ca2ca /board/nvidia/beaver | |
| parent | d3daba10f159cca7e9d24c6f154926a9b92c75e3 (diff) | |
| download | u-boot-imx-b5e01eecc89e3e5c2ed3c17b803529be3c3702fb.zip u-boot-imx-b5e01eecc89e3e5c2ed3c17b803529be3c3702fb.tar.gz u-boot-imx-b5e01eecc89e3e5c2ed3c17b803529be3c3702fb.tar.bz2 | |
ARM: AM43xx: GP_EVM: Add support for DDR3
GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH).
Adding details for the same.
Below is the brief description of DDR3 init sequence(SW leveling):
-> Enable VTT regulator
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program leveling registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'board/nvidia/beaver')
0 files changed, 0 insertions, 0 deletions