Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx

4 files changed, 55 insertions, 55 deletions

diff --git a/board/netstal/common/fixed_sdram.c b/board/netstal/common/fixed_sdram.c
index f7baed6..2f21fbb 100644
--- a/board/netstal/common/fixed_sdram.c
+++ b/board/netstal/common/fixed_sdram.c
@@ -29,17 +29,17 @@ void show_sdram_registers(void)
 	u32 value;
 
 	printf("SDRAM Controller Registers --\n");
-	mfsdram(mem_mcopt1, value);
+	mfsdram(SDRAM0_CFG, value);
 	printf("    SDRAM0_CFG   : 0x%08x\n", value);
-	mfsdram(mem_status, value);
+	mfsdram(SDRAM0_STATUS, value);
 	printf("    SDRAM0_STATUS: 0x%08x\n", value);
-	mfsdram(mem_mb0cf, value);
+	mfsdram(SDRAM0_B0CR, value);
 	printf("    SDRAM0_B0CR  : 0x%08x\n", value);
-	mfsdram(mem_mb1cf, value);
+	mfsdram(SDRAM0_B1CR, value);
 	printf("    SDRAM0_B1CR  : 0x%08x\n", value);
-	mfsdram(mem_sdtr1, value);
+	mfsdram(SDRAM0_TR, value);
 	printf("    SDRAM0_TR    : 0x%08x\n", value);
-	mfsdram(mem_rtr, value);
+	mfsdram(SDRAM0_RTR, value);
 	printf("    SDRAM0_RTR   : 0x%08x\n", value);
 }
 #endif
@@ -50,53 +50,53 @@ long int init_ppc405_sdram(unsigned int dram_size)
 	printf(__FUNCTION__);
 #endif
 	/* disable memory controller */
-	mtsdram(mem_mcopt1, 0x00000000);
+	mtsdram(SDRAM0_CFG, 0x00000000);
 
 	udelay (500);
 
 	/* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
-	mtsdram(mem_besra, 0xffffffff);
+	mtsdram(SDRAM0_BESR0, 0xffffffff);
 
 	/* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
-	mtsdram(mem_besrb, 0xffffffff);
+	mtsdram(SDRAM0_BESR1, 0xffffffff);
 
 	/* Clear SDRAM0_ECCCFG (disable ECC) */
-	mtsdram(mem_ecccf, 0x00000000);
+	mtsdram(SDRAM0_ECCCFG, 0x00000000);
 
 	/* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
-	mtsdram(mem_eccerr, 0xffffffff);
+	mtsdram(SDRAM0_ECCESR, 0xffffffff);
 
 	/* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2
 	 */
-	mtsdram(mem_sdtr1, 0x008a4015);
+	mtsdram(SDRAM0_TR, 0x008a4015);
 
 	/* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1
 	 * and refresh timer
 	 */
 	switch (dram_size >> 20) {
 	case 32:
-		mtsdram(mem_mb0cf, 0x00062001);
-		mtsdram(mem_rtr,   0x07F00000);
+		mtsdram(SDRAM0_B0CR, 0x00062001);
+		mtsdram(SDRAM0_RTR,   0x07F00000);
 		break;
 	case 64:
-		mtsdram(mem_mb0cf, 0x00084001);
-		mtsdram(mem_rtr,   0x04100000);
+		mtsdram(SDRAM0_B0CR, 0x00084001);
+		mtsdram(SDRAM0_RTR,   0x04100000);
 		break;
 	case 128:
-		mtsdram(mem_mb0cf, 0x000A4001);
-		mtsdram(mem_rtr,   0x04100000);
+		mtsdram(SDRAM0_B0CR, 0x000A4001);
+		mtsdram(SDRAM0_RTR,   0x04100000);
 		break;
 	default:
 		printf("Invalid memory size of %d MB given\n", dram_size >> 20);
 	}
 
 	/* Power management idle timer set to the default. */
-	mtsdram(mem_pmit, 0x07c00000);
+	mtsdram(SDRAM0_PMIT, 0x07c00000);
 
 	udelay (500);
 
 	/* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) TODO */
-	mtsdram(mem_mcopt1, 0x90800000);
+	mtsdram(SDRAM0_CFG, 0x90800000);
 
 #ifdef DEBUG
 	printf("%s: done\n", __FUNCTION__);
diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c
index 40bec8e..ba3e9c3 100644
--- a/board/netstal/hcu4/hcu4.c
+++ b/board/netstal/hcu4/hcu4.c
@@ -58,12 +58,12 @@ int board_early_init_f (void)
 	 *      IRQ 17-24 RESERVED/UNUSED
 	 *      IRQ 31 (EXT IRQ 6) (unused)
 	 */
-	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
-	mtdcr(uicer, 0x00000000); /* disable all ints */
-	mtdcr(uiccr, 0x00000000); /* set all to be non-critical */
-	mtdcr(uicpr, 0xFFFFE000); /* set int polarities */
-	mtdcr(uictr, 0x00000000); /* set int trigger levels */
-	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+	mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
+	mtdcr(UIC0PR, 0xFFFFE000); /* set int polarities */
+	mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
+	mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
 
 	mtdcr(CPC0_CR1, CPC0_CR1_VALUE);
 	mtdcr(CPC0_ECR, 0x60606000);
diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c
index 836c034..4522612 100644
--- a/board/netstal/hcu5/hcu5.c
+++ b/board/netstal/hcu5/hcu5.c
@@ -129,29 +129,29 @@ int board_early_init_f(void)
 	/*
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 */
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
-	mtdcr(uic0er, 0x00000000);	/* disable all */
-	mtdcr(uic0cr, 0x00000005);	/* ATI & UIC1 crit are critical */
-	mtdcr(uic0pr, 0xfffff7ff);	/* per ref-board manual */
-	mtdcr(uic0tr, 0x00000000);	/* per ref-board manual */
-	mtdcr(uic0vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
-
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
-	mtdcr(uic1er, 0x00000000);	/* disable all */
-	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic1pr, 0xffffffff);	/* per ref-board manual */
-	mtdcr(uic1tr, 0x00000000);	/* per ref-board manual */
-	mtdcr(uic1vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
-
-	mtdcr(uic2sr, 0xffffffff);	/* clear all */
-	mtdcr(uic2er, 0x00000000);	/* disable all */
-	mtdcr(uic2cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic2pr, 0xffffffff);	/* per ref-board manual */
-	mtdcr(uic2tr, 0x00000000);	/* per ref-board manual */
-	mtdcr(uic2vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic2sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xfffff7ff);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC2ER, 0x00000000);	/* disable all */
+	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
 	mtsdr(SDR0_PFC0, 0x00003E00);	/* Pin function:  */
 	mtsdr(SDR0_PFC1, 0x00848000);	/* Pin function: UART0 has 4 pins */
 
diff --git a/board/netstal/mcu25/mcu25.c b/board/netstal/mcu25/mcu25.c
index 9054282..945d79a 100644
--- a/board/netstal/mcu25/mcu25.c
+++ b/board/netstal/mcu25/mcu25.c
@@ -64,12 +64,12 @@ int board_early_init_f (void)
 	 *      IRQ 17-24 RESERVED/UNUSED
 	 *      IRQ 31 (EXT IRQ 6) (unused)
 	 */
-	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
-	mtdcr(uicer, 0x00000000); /* disable all ints */
-	mtdcr(uiccr, 0x00000000); /* set all to be non-critical */
-	mtdcr(uicpr, 0xFFFFE000); /* set int polarities */
-	mtdcr(uictr, 0x00000000); /* set int trigger levels */
-	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+	mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
+	mtdcr(UIC0PR, 0xFFFFE000); /* set int polarities */
+	mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
+	mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
 
 	mtdcr(CPC0_CR1, CPC0_CR1_VALUE);
 	mtdcr(CPC0_ECR, 0x60606000);