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| author | Wolfgang Denk <wd@denx.de> | 2010-04-24 21:16:57 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2010-04-24 21:16:57 +0200 |
| commit | a77034a8dfc7942ca08483138dccdebeacc36826 (patch) | |
| tree | cecf2628651fb6fafd22ac7b9d6cd3f3770df2b6 /board/netstal | |
| parent | 500fbae2043532275e09a8666d837d052c9bad9a (diff) | |
| parent | cf6eb6da433179674571f9370566b1ec8989a41a (diff) | |
| download | u-boot-imx-a77034a8dfc7942ca08483138dccdebeacc36826.zip u-boot-imx-a77034a8dfc7942ca08483138dccdebeacc36826.tar.gz u-boot-imx-a77034a8dfc7942ca08483138dccdebeacc36826.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
Diffstat (limited to 'board/netstal')
| -rw-r--r-- | board/netstal/hcu5/init.S | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/board/netstal/hcu5/init.S b/board/netstal/hcu5/init.S index 05b5e38..45e63dd 100644 --- a/board/netstal/hcu5/init.S +++ b/board/netstal/hcu5/init.S @@ -40,13 +40,13 @@ tlbtab: tlbtab_start /* TLB#0: vxWorks needs this entry for the Machine Check interrupt, */ - tlbentry( 0x40000000, SZ_256M, 0, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( 0x40000000, SZ_256M, 0, 0, AC_RWX | SA_IG ) /* TLB#1: TLB-entry for DDR SDRAM (Up to 2GB) */ tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, - AC_R|AC_W|AC_X|SA_G|SA_I ) + AC_RWX | SA_IG ) /* TLB#2: TLB-entry for EBC */ - tlbentry( 0x80000000, SZ_256M, 0x80000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( 0x80000000, SZ_256M, 0x80000000, 1, AC_RWX | SA_IG) /* * TLB#3: BOOT_CS (FLASH) must be forth. Before relocation SA_I can be @@ -54,7 +54,7 @@ tlbtab: * to enable SA_I */ tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_1M, CONFIG_SYS_BOOT_BASE_ADDR, 1, - AC_R|AC_W|AC_X|SA_G) + AC_RWX | SA_G) /* * TLB entries for SDRAM are not needed on this platform. @@ -64,43 +64,43 @@ tlbtab: /* TLB#4: */ tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, - AC_R|AC_W|SA_G|SA_I ) + AC_RW | SA_IG ) /* TLB#5: */ tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, - AC_R|AC_W|SA_G|SA_I ) + AC_RW | SA_IG ) /* TLB#6: */ tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, - AC_R|AC_W|SA_G|SA_I ) + AC_RW | SA_IG ) /* TLB-entry for Internal Registers & OCM */ /* TLB#7: */ tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, - AC_R|AC_W|AC_X|SA_G|SA_I ) + AC_RWX | SA_IG ) /*TLB-entry PCI registers*/ /* TLB#8: */ - tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG ) /* TLB-entry for peripherals */ /* TLB#9: */ - tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG) /* CAN */ /* TLB#10: */ - tlbentry( CONFIG_SYS_CS_1, SZ_1K, CONFIG_SYS_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_CS_1, SZ_1K, CONFIG_SYS_CS_1, 1, AC_RWX | SA_IG ) /* TLB#11: CPLD and IMC-Standard 32 MB */ - tlbentry( CONFIG_SYS_CS_2, SZ_16M, CONFIG_SYS_CS_2, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_CS_2, SZ_16M, CONFIG_SYS_CS_2, 1, AC_RWX | SA_IG ) /* TLB#12: */ tlbentry( CONFIG_SYS_CS_2 + 0x1000000, SZ_16M, CONFIG_SYS_CS_2 + 0x1000000, 1, - AC_R|AC_W|AC_X|SA_G|SA_I ) + AC_RWX | SA_IG ) /* IMC-Fast 32 MB */ /* TLB#13: */ - tlbentry( CONFIG_SYS_CS_3, SZ_16M, CONFIG_SYS_CS_3, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_CS_3, SZ_16M, CONFIG_SYS_CS_3, 1, AC_RWX | SA_IG ) /* TLB#14: */ tlbentry( CONFIG_SYS_CS_3 + 0x1000000, SZ_16M, CONFIG_SYS_CS_3, 1, - AC_R|AC_W|AC_X|SA_G|SA_I ) + AC_RWX | SA_IG ) tlbtab_end |