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authorStefan Roese <sr@denx.de>2008-10-21 11:43:08 +0200
committerStefan Roese <sr@denx.de>2008-10-21 11:43:08 +0200
commitf61f1e150c84f5b9347fca79a4bc5f2286c545d2 (patch)
treeab90f076f18e56b2b3e8c9375b95917daa78c1d9 /board/netstal/hcu5/sdram.c
parentec081c2c190148b374e86a795fb6b1c49caeb549 (diff)
parentf82642e33899766892499b163e60560fbbf87773 (diff)
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Merge branch 'master' of /home/stefan/git/u-boot/u-boot
Diffstat (limited to 'board/netstal/hcu5/sdram.c')
-rw-r--r--board/netstal/hcu5/sdram.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c
index e5df62e..f59bd7d 100644
--- a/board/netstal/hcu5/sdram.c
+++ b/board/netstal/hcu5/sdram.c
@@ -263,20 +263,20 @@ phys_size_t initdram (int board_type)
/*
* Program tlb entries for this size (dynamic)
*/
- remove_tlb(CFG_SDRAM_BASE, 256 << 20);
+ remove_tlb(CONFIG_SYS_SDRAM_BASE, 256 << 20);
program_tlb(0, 0, dram_size, TLB_WORD2_W_ENABLE | TLB_WORD2_I_ENABLE);
/*
* Setup 2nd TLB with same physical address but different virtual
* address with cache enabled. This is done for fast ECC generation.
*/
- program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0);
+ program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, dram_size, 0);
#ifdef CONFIG_DDR_ECC
/*
* If ECC is enabled, initialize the parity bits.
*/
- program_ecc(CFG_DDR_CACHED_ADDR, dram_size);
+ program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, dram_size);
#endif
return (dram_size);