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| author | Wolfgang Denk <wd@denx.de> | 2008-06-11 22:13:07 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-06-11 22:13:07 +0200 |
| commit | 1730edf76c54381475e2da11f75b1ce563c4e62c (patch) | |
| tree | 1f2a9fb7a7cd9b547374d9cc3715a7f18001e1ee /board/netstal/hcu5/sdram.c | |
| parent | 5ea67393b8b554b8165c38912d753a8df043020d (diff) | |
| parent | b2815f79288d4da7a3ba18bdbd05120ce09d5622 (diff) | |
| download | u-boot-imx-1730edf76c54381475e2da11f75b1ce563c4e62c.zip u-boot-imx-1730edf76c54381475e2da11f75b1ce563c4e62c.tar.gz u-boot-imx-1730edf76c54381475e2da11f75b1ce563c4e62c.tar.bz2 | |
Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx
Diffstat (limited to 'board/netstal/hcu5/sdram.c')
| -rw-r--r-- | board/netstal/hcu5/sdram.c | 26 |
1 files changed, 2 insertions, 24 deletions
diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index 6b1b53a..d8817b8 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -40,28 +40,6 @@ void hcu_led_set(u32 value); void dcbz_area(u32 start_address, u32 num_bytes); -#define DDR_DCR_BASE 0x10 -#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */ -#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */ - -#define DDR0_01_INT_MASK_MASK 0x000000FF -#define DDR0_00_INT_ACK_ALL 0x7F000000 -#define DDR0_01_INT_MASK_ALL_ON 0x000000FF -#define DDR0_01_INT_MASK_ALL_OFF 0x00000000 - -#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */ -#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000 -#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000 - -#define DDR0_22 0x16 -/* ECC */ -#define DDR0_22_CTRL_RAW_MASK 0x03000000 -#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not enabled */ -#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC no correction */ -#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* Not a ECC RAM*/ -#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC correcting on */ -#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7) - #define ECC_RAM 0x03267F0B #define NO_ECC_RAM 0x00267F0B @@ -111,11 +89,11 @@ static int wait_for_dlllock(void) /* -----------------------------------------------------------+ * Wait for the DCC master delay line to finish calibration * ----------------------------------------------------------*/ - mtdcr(ddrcfga, DDR0_17); + mtdcr(memcfga, DDR0_17); val = DDR0_17_DLLLOCKREG_UNLOCKED; while (wait != 0xffff) { - val = mfdcr(ddrcfgd); + val = mfdcr(memcfgd); if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED) /* dlllockreg bit on */ |