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authorStefan Roese <sr@denx.de>2009-11-12 12:00:49 +0100
committerStefan Roese <sr@denx.de>2009-11-19 11:35:08 +0100
commit1095493a5d4c16f481a783f6f54d83ad0e07dfa0 (patch)
treed94be4d3a2e4466ef0a6780616a82c2599df20cb /board/netstal/hcu5/hcu5.c
parent06f43286c6354aaab0103615e83893512f86eee7 (diff)
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ppc4xx: Consolidate pci_target_init() function
This patch removes the duplicted implementations of the pci_target_init() function by introducing a weak default function for it. This weak default has a different implementation for 440EP(x)/GR(x) PPC's. It can be overridden by a board specific version (e.g. PMC440, korat). Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Diffstat (limited to 'board/netstal/hcu5/hcu5.c')
-rw-r--r--board/netstal/hcu5/hcu5.c65
1 files changed, 0 insertions, 65 deletions
diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c
index 7ffc262..144fdd9 100644
--- a/board/netstal/hcu5/hcu5.c
+++ b/board/netstal/hcu5/hcu5.c
@@ -377,71 +377,6 @@ int pci_pre_init(struct pci_controller *hose)
}
/*
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- */
-void pci_target_init(struct pci_controller *hose)
-{
- if (!board_with_pci()) { return; }
- /*
- * Set up Direct MMIO registers
- *
- * PowerPC440EPX PCI Master configuration.
- * Map one 1Gig range of PLB/processor addresses to PCI memory space.
- * PLB address 0xA0000000-0xDFFFFFFF ==> PCI address
- * 0xA0000000-0xDFFFFFFF
- * Use byte reversed out routines to handle endianess.
- * Make this region non-prefetchable.
- */
- /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIL0_PMM0MA, 0x00000000);
- out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
- out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- /* 512M + No prefetching, and enable region */
- out32r(PCIL0_PMM0MA, 0xE0000001);
-
- /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIL0_PMM1MA, 0x00000000);
- out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
- /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
- out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
- /* 512M + No prefetching, and enable region */
- out32r(PCIL0_PMM1MA, 0xE0000001);
-
- out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
- out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
- out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
-
- /*
- * Set up Configuration registers
- */
-
- /* Program the board's subsystem id/vendor id */
- pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
- CONFIG_SYS_PCI_SUBSYS_VENDORID);
- pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
-
- /* Configure command register as bus master */
- pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
- /* 240nS PCI clock */
- pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
- /* No error reporting */
- pci_write_config_word(0, PCI_ERREN, 0);
-
- pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-}
-
-/*
* pci_master_init
*
*/