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| author | Wolfgang Denk <wd@pollux.denx.de> | 2006-05-03 01:24:04 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@pollux.denx.de> | 2006-05-03 01:24:04 +0200 |
| commit | 610cf3676ee7376e0a55419626a30414a7b20db2 (patch) | |
| tree | 31d7b61fbfd7421441d44d0c47c580c722c69465 /board/nc650/nand.c | |
| parent | da4849fb30db9ec2cb1ae0bafa7455b9c4cb87b3 (diff) | |
| download | u-boot-imx-610cf3676ee7376e0a55419626a30414a7b20db2.zip u-boot-imx-610cf3676ee7376e0a55419626a30414a7b20db2.tar.gz u-boot-imx-610cf3676ee7376e0a55419626a30414a7b20db2.tar.bz2 | |
Coding Style cleanup
Diffstat (limited to 'board/nc650/nand.c')
| -rw-r--r-- | board/nc650/nand.c | 68 |
1 files changed, 34 insertions, 34 deletions
diff --git a/board/nc650/nand.c b/board/nc650/nand.c index f27e536..de54386 100644 --- a/board/nc650/nand.c +++ b/board/nc650/nand.c @@ -37,22 +37,22 @@ static void nc650_hwcontrol(struct mtd_info *mtd, int cmd) struct nand_chip *this = mtd->priv; switch(cmd) { - case NAND_CTL_SETCLE: - this->IO_ADDR_W += 2; - break; - case NAND_CTL_CLRCLE: - this->IO_ADDR_W -= 2; - break; - case NAND_CTL_SETALE: - this->IO_ADDR_W += 1; - break; - case NAND_CTL_CLRALE: - this->IO_ADDR_W -= 1; - break; - case NAND_CTL_SETNCE: - case NAND_CTL_CLRNCE: - /* nop */ - break; + case NAND_CTL_SETCLE: + this->IO_ADDR_W += 2; + break; + case NAND_CTL_CLRCLE: + this->IO_ADDR_W -= 2; + break; + case NAND_CTL_SETALE: + this->IO_ADDR_W += 1; + break; + case NAND_CTL_CLRALE: + this->IO_ADDR_W -= 1; + break; + case NAND_CTL_SETNCE: + case NAND_CTL_CLRNCE: + /* nop */ + break; } } #elif defined(CONFIG_IDS852_REV2) @@ -64,24 +64,24 @@ static void nc650_hwcontrol(struct mtd_info *mtd, int cmd) struct nand_chip *this = mtd->priv; switch(cmd) { - case NAND_CTL_SETCLE: - *(((volatile __u8 *) this->IO_ADDR_W) + 0xa) = 0; - break; - case NAND_CTL_CLRCLE: - *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0; - break; - case NAND_CTL_SETALE: - *(((volatile __u8 *) this->IO_ADDR_W) + 0x9) = 0; - break; - case NAND_CTL_CLRALE: - *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0; - break; - case NAND_CTL_SETNCE: - *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0; - break; - case NAND_CTL_CLRNCE: - *(((volatile __u8 *) this->IO_ADDR_W) + 0xc) = 0; - break; + case NAND_CTL_SETCLE: + *(((volatile __u8 *) this->IO_ADDR_W) + 0xa) = 0; + break; + case NAND_CTL_CLRCLE: + *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0; + break; + case NAND_CTL_SETALE: + *(((volatile __u8 *) this->IO_ADDR_W) + 0x9) = 0; + break; + case NAND_CTL_CLRALE: + *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0; + break; + case NAND_CTL_SETNCE: + *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0; + break; + case NAND_CTL_CLRNCE: + *(((volatile __u8 *) this->IO_ADDR_W) + 0xc) = 0; + break; } } #else |