summaryrefslogtreecommitdiff
path: root/board/mucmc52
diff options
context:
space:
mode:
authorWolfgang Denk <wd@denx.de>2008-09-13 02:23:05 +0200
committerWolfgang Denk <wd@denx.de>2008-09-13 02:23:05 +0200
commitf12e4549b6fb01cd2654348af95a3c7a6ac161e7 (patch)
tree725ff6a5ad3b615b0e94c42bc2834a9e70f18d8e /board/mucmc52
parent0c32565f536609d78feef35c88bbc39d3ac53a73 (diff)
downloadu-boot-imx-f12e4549b6fb01cd2654348af95a3c7a6ac161e7.zip
u-boot-imx-f12e4549b6fb01cd2654348af95a3c7a6ac161e7.tar.gz
u-boot-imx-f12e4549b6fb01cd2654348af95a3c7a6ac161e7.tar.bz2
Coding style cleanup, update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'board/mucmc52')
-rw-r--r--board/mucmc52/mucmc52.c68
1 files changed, 34 insertions, 34 deletions
diff --git a/board/mucmc52/mucmc52.c b/board/mucmc52/mucmc52.c
index ae3ca24..74417c4 100644
--- a/board/mucmc52/mucmc52.c
+++ b/board/mucmc52/mucmc52.c
@@ -192,22 +192,22 @@ phys_size_t initdram (int board_type)
#endif /* CFG_RAMBOOT */
/*
- * On MPC5200B we need to set the special configuration delay in the
- * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
- * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
- *
- * "The SDelay should be written to a value of 0x00000004. It is
- * required to account for changes caused by normal wafer processing
- * parameters."
- */
- svr = get_svr();
- pvr = get_pvr();
- if ((SVR_MJREV(svr) >= 2) &&
- (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
-
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_SDELAY, 0x04);
- __asm__ volatile ("sync");
- }
+ * On MPC5200B we need to set the special configuration delay in the
+ * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+ * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+ *
+ * "The SDelay should be written to a value of 0x00000004. It is
+ * required to account for changes caused by normal wafer processing
+ * parameters."
+ */
+ svr = get_svr();
+ pvr = get_pvr();
+ if ((SVR_MJREV(svr) >= 2) &&
+ (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+
+ out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_SDELAY, 0x04);
+ __asm__ volatile ("sync");
+ }
return dramsize + dramsize2;
}
@@ -339,14 +339,14 @@ int misc_init_r (void)
free (str);
#endif /* CONFIG_PREBOOT */
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x38), ' ');
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x39), ' ');
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3A), ' ');
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3B), ' ');
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3C), ' ');
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3D), ' ');
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3E), ' ');
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3F), ' ');
+ out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x38), ' ');
+ out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x39), ' ');
+ out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3A), ' ');
+ out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3B), ' ');
+ out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3C), ' ');
+ out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3D), ' ');
+ out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3E), ' ');
+ out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3F), ' ');
return 0;
}
@@ -365,16 +365,16 @@ int board_early_init_r (void)
int last_stage_init (void)
{
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x38), 'M');
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x39), 'U');
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3A), 'C');
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3B), '.');
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3C), 'M');
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3D), 'C');
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3E), '5');
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3F), '2');
-
- return 0;
+ out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x38), 'M');
+ out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x39), 'U');
+ out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3A), 'C');
+ out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3B), '.');
+ out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3C), 'M');
+ out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3D), 'C');
+ out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3E), '5');
+ out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3F), '2');
+
+ return 0;
}
#if defined(CONFIG_HW_WATCHDOG)