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| author | Fabio Estevam <fabio.estevam@nxp.com> | 2016-07-18 10:19:28 -0300 |
|---|---|---|
| committer | Peng Fan <peng.fan@nxp.com> | 2016-09-18 17:31:50 +0800 |
| commit | 697f9ffc0eea9facf2fdaf596f008560db42ea7d (patch) | |
| tree | 2b670311ae489fac742a84e98fe2df84b65edc70 /board/ms7750se | |
| parent | 505e899ce582118da28ca1f4487ce7f179225bd7 (diff) | |
| download | u-boot-imx-697f9ffc0eea9facf2fdaf596f008560db42ea7d.zip u-boot-imx-697f9ffc0eea9facf2fdaf596f008560db42ea7d.tar.gz u-boot-imx-697f9ffc0eea9facf2fdaf596f008560db42ea7d.tar.bz2 | |
mx6: clock: Fix the logic for reading axi_alt_sel
According to the IMX6DQRM Reference Manual, the description
of bit 7 (axi_alt_sel) of the CCM_CBCDR register is:
"AXI alternative clock select
0 pll2 396MHz PFD will be selected as alternative clock for AXI root clock
1 pll3 540MHz PFD will be selected as alternative clock for AXI root clock "
The current logic is inverted, so fix it to match the reference manual.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
(cherry picked from commit 8f2e2f15ffa1bb03b6e6e189312426059f3215d1)
Diffstat (limited to 'board/ms7750se')
0 files changed, 0 insertions, 0 deletions