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| author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2008-12-20 19:29:48 +0100 |
|---|---|---|
| committer | Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | 2009-01-16 10:22:26 +0900 |
| commit | e4430779623af500de1cee7892c379f07ef59813 (patch) | |
| tree | 74942b62e37730488c59603d19f045de10c92c1e /board/ms7750se | |
| parent | 85cb052ee41675ca361e6a4c69455dc715c8f2d9 (diff) | |
| download | u-boot-imx-e4430779623af500de1cee7892c379f07ef59813.zip u-boot-imx-e4430779623af500de1cee7892c379f07ef59813.tar.gz u-boot-imx-e4430779623af500de1cee7892c379f07ef59813.tar.bz2 | |
sh: lowlevel_init coding style cleanup
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'board/ms7750se')
| -rw-r--r-- | board/ms7750se/lowlevel_init.S | 150 |
1 files changed, 75 insertions, 75 deletions
diff --git a/board/ms7750se/lowlevel_init.S b/board/ms7750se/lowlevel_init.S index d3e3cd5..de05dd9 100644 --- a/board/ms7750se/lowlevel_init.S +++ b/board/ms7750se/lowlevel_init.S @@ -31,118 +31,118 @@ #include <asm/processor.h> #ifdef CONFIG_CPU_SH7751 -#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */ -#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */ +#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */ +#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */ #ifdef CONFIG_MARUBUN_PCCARD -#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15 - A3:2 A2:15 A1:15 A0:6 A0B:7 */ +#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15 + A3:2 A2:15 A1:15 A0:6 A0B:7 */ #else /* CONFIG_MARUBUN_PCCARD */ -#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15 - A3:2 A2:15 A1:15 A0:6 A0B:7 */ +#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15 + A3:2 A2:15 A1:15 A0:6 A0B:7 */ #endif /* CONFIG_MARUBUN_PCCARD */ -#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3 - A2: 1-3 A1: 1-3 A0: 0-1 */ -#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */ -#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */ -#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, ... */ -#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */ +#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3 + A2: 1-3 A1: 1-3 A0: 0-1 */ +#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */ +#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */ +#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, .. */ +#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */ #else /* CONFIG_CPU_SH7751 */ -#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */ -#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */ -#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15 - A3:2 A2:15 A1:15 A0:15 A0B:7 */ -#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3 - A2: 1-3 A1: 1-3 A0: 0-1 */ -#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */ -#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */ -#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, ... */ -#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */ +#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */ +#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */ +#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15 + A3:2 A2:15 A1:15 A0:15 A0B:7 */ +#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3 + A2: 1-3 A1: 1-3 A0: 0-1 */ +#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */ +#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */ +#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, .. */ +#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */ #endif /* CONFIG_CPU_SH7751 */ .global lowlevel_init .text - .align 2 + .align 2 lowlevel_init: - mov.l CCR_A, r1 ! CCR Address - mov.l CCR_D_DISABLE, r0 ! CCR Data - mov.l r0, @r1 + mov.l CCR_A, r1 ! CCR Address + mov.l CCR_D_DISABLE, r0 ! CCR Data + mov.l r0, @r1 init_bsc: - mov.l FRQCR_A,r1 /* FRQCR Address */ - mov.l FRQCR_D,r0 /* FRQCR Data */ - mov.w r0,@r1 + mov.l FRQCR_A, r1 /* FRQCR Address */ + mov.l FRQCR_D, r0 /* FRQCR Data */ + mov.w r0, @r1 - mov.l BCR1_A,r1 /* BCR1 Address */ - mov.l BCR1_D,r0 /* BCR1 Data */ - mov.l r0,@r1 + mov.l BCR1_A, r1 /* BCR1 Address */ + mov.l BCR1_D, r0 /* BCR1 Data */ + mov.l r0, @r1 - mov.l BCR2_A,r1 /* BCR2 Address */ - mov.l BCR2_D,r0 /* BCR2 Data */ - mov.w r0,@r1 + mov.l BCR2_A, r1 /* BCR2 Address */ + mov.l BCR2_D, r0 /* BCR2 Data */ + mov.w r0, @r1 - mov.l WCR1_A,r1 /* WCR1 Address */ - mov.l WCR1_D,r0 /* WCR1 Data */ - mov.l r0,@r1 + mov.l WCR1_A, r1 /* WCR1 Address */ + mov.l WCR1_D, r0 /* WCR1 Data */ + mov.l r0, @r1 - mov.l WCR2_A,r1 /* WCR2 Address */ - mov.l WCR2_D,r0 /* WCR2 Data */ - mov.l r0,@r1 + mov.l WCR2_A, r1 /* WCR2 Address */ + mov.l WCR2_D, r0 /* WCR2 Data */ + mov.l r0, @r1 - mov.l WCR3_A,r1 /* WCR3 Address */ - mov.l WCR3_D,r0 /* WCR3 Data */ - mov.l r0,@r1 + mov.l WCR3_A, r1 /* WCR3 Address */ + mov.l WCR3_D, r0 /* WCR3 Data */ + mov.l r0, @r1 - mov.l MCR_A,r1 /* MCR Address */ - mov.l MCR_D1,r0 /* MCR Data1 */ - mov.l r0,@r1 + mov.l MCR_A, r1 /* MCR Address */ + mov.l MCR_D1, r0 /* MCR Data1 */ + mov.l r0, @r1 - mov.l SDMR3_A,r1 /* Set SDRAM mode */ - mov #0,r0 - mov.b r0,@r1 + mov.l SDMR3_A, r1 /* Set SDRAM mode */ + mov #0, r0 + mov.b r0, @r1 ! Do you need PCMCIA setting? ! If so, please add the lines here... - mov.l RTCNT_A,r1 /* RTCNT Address */ - mov.l RTCNT_D,r0 /* RTCNT Data */ - mov.w r0,@r1 + mov.l RTCNT_A, r1 /* RTCNT Address */ + mov.l RTCNT_D, r0 /* RTCNT Data */ + mov.w r0, @r1 - mov.l RTCOR_A,r1 /* RTCOR Address */ - mov.l RTCOR_D,r0 /* RTCOR Data */ - mov.w r0,@r1 + mov.l RTCOR_A, r1 /* RTCOR Address */ + mov.l RTCOR_D, r0 /* RTCOR Data */ + mov.w r0, @r1 - mov.l RTCSR_A,r1 /* RTCSR Address */ - mov.l RTCSR_D,r0 /* RTCSR Data */ - mov.w r0,@r1 + mov.l RTCSR_A, r1 /* RTCSR Address */ + mov.l RTCSR_D, r0 /* RTCSR Data */ + mov.w r0, @r1 - mov.l RFCR_A,r1 /* RFCR Address */ - mov.l RFCR_D,r0 /* RFCR Data */ - mov.w r0,@r1 /* Clear reflesh counter */ + mov.l RFCR_A, r1 /* RFCR Address */ + mov.l RFCR_D, r0 /* RFCR Data */ + mov.w r0, @r1 /* Clear reflesh counter */ /* Wait DRAM refresh 30 times */ - mov #30,r3 + mov #30, r3 1: - mov.w @r1,r0 - extu.w r0,r2 - cmp/hi r3,r2 + mov.w @r1, r0 + extu.w r0, r2 + cmp/hi r3, r2 bf 1b - mov.l MCR_A,r1 /* MCR Address */ - mov.l MCR_D2,r0 /* MCR Data2 */ - mov.l r0,@r1 + mov.l MCR_A, r1 /* MCR Address */ + mov.l MCR_D2, r0 /* MCR Data2 */ + mov.l r0, @r1 - mov.l SDMR3_A,r1 /* Set SDRAM mode */ - mov #0,r0 - mov.b r0,@r1 + mov.l SDMR3_A, r1 /* Set SDRAM mode */ + mov #0, r0 + mov.b r0, @r1 rts - nop + nop .align 2 -CCR_A: .long CCR -CCR_D_DISABLE: .long 0x0808 +CCR_A: .long CCR +CCR_D_DISABLE: .long 0x0808 FRQCR_A: .long FRQCR FRQCR_D: #ifdef CONFIG_CPU_TYPE_R |