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author | wdenk <wdenk> | 2003-06-19 23:01:32 +0000 |
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committer | wdenk <wdenk> | 2003-06-19 23:01:32 +0000 |
commit | 48b42616e928ce6eacfe20276a1614e2b27ac4b5 (patch) | |
tree | 0c194fbd1059185f158c0b37dc3c846b50c2ee2f /board/mpl | |
parent | 15ef8a5d17181ea376fac94579dce0af1cfcdeb7 (diff) | |
download | u-boot-imx-48b42616e928ce6eacfe20276a1614e2b27ac4b5.zip u-boot-imx-48b42616e928ce6eacfe20276a1614e2b27ac4b5.tar.gz u-boot-imx-48b42616e928ce6eacfe20276a1614e2b27ac4b5.tar.bz2 |
* Patches by David M�ller, 12 Jun 2003:
- rewrite of the S3C24X0 register definitions stuff
- "driver" for the built-in S3C24X0 RTC
* Patches by Yuli Barcohen, 12 Jun 2003:
- Add MII support and Ethernet PHY initialization for MPC8260ADS board
- Fix incorrect SIUMCR initialisation caused by wrong Hard Reset
configuration word supplied by FPGA on some MPC8260ADS boards
* Patch by Pantelis Antoniou, 10 Jun 2003:
Unify status LED interface
Diffstat (limited to 'board/mpl')
-rw-r--r-- | board/mpl/common/common_util.c | 4 | ||||
-rw-r--r-- | board/mpl/vcma9/config.mk | 4 | ||||
-rw-r--r-- | board/mpl/vcma9/memsetup.S | 12 | ||||
-rw-r--r-- | board/mpl/vcma9/vcma9.c | 95 | ||||
-rw-r--r-- | board/mpl/vcma9/vcma9.h | 88 |
5 files changed, 171 insertions, 32 deletions
diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c index aa2ba6f..503654e 100644 --- a/board/mpl/common/common_util.c +++ b/board/mpl/common/common_util.c @@ -45,7 +45,11 @@ extern int gunzip (void *, int, unsigned char *, int *); extern int mem_test(unsigned long start, unsigned long ramsize, int quiet); #define I2C_BACKUP_ADDR 0x7C00 /* 0x200 bytes for backup */ +#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) #define IMAGE_SIZE 0x80000 +#elif defined(CONFIG_VCMA9) +#define IMAGE_SIZE 0x40000 /* ugly, but it works for now */ +#endif extern flash_info_t flash_info[]; /* info for FLASH chips */ diff --git a/board/mpl/vcma9/config.mk b/board/mpl/vcma9/config.mk index 19ef187..95d69cc 100644 --- a/board/mpl/vcma9/config.mk +++ b/board/mpl/vcma9/config.mk @@ -15,10 +15,10 @@ # Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 # optionally with a ramdisk at 3080'0000 # -# we load ourself to 33F0'0000 +# we load ourself to 33F8'0000 # # download area is 3300'0000 # -TEXT_BASE = 0x33F00000 +TEXT_BASE = 0x33F80000 diff --git a/board/mpl/vcma9/memsetup.S b/board/mpl/vcma9/memsetup.S index 80721cd..557e554 100644 --- a/board/mpl/vcma9/memsetup.S +++ b/board/mpl/vcma9/memsetup.S @@ -54,8 +54,10 @@ /* BANK0CON */ #define B0_Tacs 0x0 /* 0clk */ -#define B0_Tcos 0x0 /* 0clk */ -#define B0_Tacc 0x5 /* 8clk */ +#define B0_Tcos 0x1 /* 1clk */ +/*#define B0_Tcos 0x0 0clk */ +#define B0_Tacc 0x7 /* 14clk */ +/*#define B0_Tacc 0x5 8clk */ #define B0_Tcoh 0x0 /* 0clk */ #define B0_Tah 0x0 /* 0clk */ #define B0_Tacp 0x0 /* page mode is not used */ @@ -63,8 +65,10 @@ /* BANK1CON */ #define B1_Tacs 0x0 /* 0clk */ -#define B1_Tcos 0x0 /* 0clk */ -#define B1_Tacc 0x5 /* 8clk */ +#define B1_Tcos 0x1 /* 1clk */ +/*#define B1_Tcos 0x0 0clk */ +#define B1_Tacc 0x7 /* 14clk */ +/*#define B1_Tacc 0x5 8clk */ #define B1_Tcoh 0x0 /* 0clk */ #define B1_Tah 0x0 /* 0clk */ #define B1_Tacp 0x0 /* page mode is not used */ diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c index 4743e6b..b051bfe 100644 --- a/board/mpl/vcma9/vcma9.c +++ b/board/mpl/vcma9/vcma9.c @@ -72,41 +72,46 @@ static inline void delay(unsigned long loops) int board_init(void) { DECLARE_GLOBAL_DATA_PTR; + S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); /* to reduce PLL lock time, adjust the LOCKTIME register */ - rLOCKTIME = 0xFFFFFF; + clk_power->LOCKTIME = 0xFFFFFF; /* configure MPLL */ - rMPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); + clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); /* some delay between MPLL and UPLL */ delay (4000); /* configure UPLL */ - rUPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); + clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); /* some delay between MPLL and UPLL */ delay (8000); /* set up the I/O ports */ - rGPACON = 0x007FFFFF; - rGPBCON = 0x002AAAAA; - rGPBUP = 0x000002BF; - rGPCCON = 0xAAAAAAAA; - rGPCUP = 0x0000FFFF; - rGPDCON = 0xAAAAAAAA; - rGPDUP = 0x0000FFFF; - rGPECON = 0xAAAAAAAA; - rGPEUP = 0x000037F7; - rGPFCON = 0x00000000; - rGPFUP = 0x00000000; - rGPGCON = 0xFFEAFF5A; - rGPGUP = 0x0000F0DC; - rGPHCON = 0x0028AAAA; - rGPHUP = 0x00000656; + gpio->GPACON = 0x007FFFFF; + gpio->GPBCON = 0x002AAAAA; + gpio->GPBUP = 0x000002BF; + gpio->GPCCON = 0xAAAAAAAA; + gpio->GPCUP = 0x0000FFFF; + gpio->GPDCON = 0xAAAAAAAA; + gpio->GPDUP = 0x0000FFFF; + gpio->GPECON = 0xAAAAAAAA; + gpio->GPEUP = 0x000037F7; + gpio->GPFCON = 0x00000000; + gpio->GPFUP = 0x00000000; + gpio->GPGCON = 0xFFEAFF5A; + gpio->GPGUP = 0x0000F0DC; + gpio->GPHCON = 0x0028AAAA; + gpio->GPHUP = 0x00000656; /* setup correct IRQ modes for NIC */ - rEXTINT2 = (rEXTINT2 & ~(7<<8)) | (4<<8); /* rising edge mode */ + gpio->EXTINT2 = (gpio->EXTINT2 & ~(7<<8)) | (4<<8); /* rising edge mode */ + + /* select USB port 2 to be host or device (fix to host for now) */ + gpio->MISCCR |= 0x08; /* init serial */ gd->baudrate = CONFIG_BAUDRATE; @@ -136,6 +141,50 @@ int dram_init(void) } /* + * NAND flash initialization. + */ +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +extern void +nand_probe(ulong physadr); + + +static inline void NF_Reset(void) +{ + int i; + + NF_SetCE(NFCE_LOW); + NF_Cmd(0xFF); /* reset command */ + for(i = 0; i < 10; i++); /* tWB = 100ns. */ + NF_WaitRB(); /* wait 200~500us; */ + NF_SetCE(NFCE_HIGH); +} + + +static inline void NF_Init(void) +{ +#define TACLS 0 +#define TWRPH0 3 +#define TWRPH1 0 + NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0)); + //nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); + // 1 1 1 1, 1 xxx, r xxx, r xxx + // En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1 + + NF_Reset(); +} + +void +nand_init(void) +{ + S3C2410_NAND * const nand = S3C2410_GetBase_NAND(); + + NF_Init(); + printf("NAND flash probing at 0x%.8lX\n", (ulong)nand); + nand_probe((ulong)nand); +} +#endif + +/* * Get some Board/PLD Info */ @@ -195,12 +244,12 @@ int checkboard(void) puts ("### No HW ID - assuming VCMA9"); } else { b->serial_name[5] = 0; - printf ("%s-%d Rev %c SN: %s", b->serial_name, Get_Board_Config(), + printf ("%s-%d PCB Rev %c SN: %s", b->serial_name, Get_Board_Config(), Get_Board_PCB(), &b->serial_name[6]); } } else { s[5] = 0; - printf ("%s-%d Rev %c SN: %s", s, Get_Board_Config(), Get_Board_PCB(), + printf ("%s-%d PCB Rev %c SN: %s", s, Get_Board_Config(), Get_Board_PCB(), &s[6]); } printf("\n"); @@ -211,7 +260,7 @@ int checkboard(void) void print_vcma9_rev(void) { - printf("Board: VCMA9-%d Rev: %c (PLD Ver: %d, Rev: %d)\n", + printf("Board: VCMA9-%d PCB Rev: %c (PLD Ver: %d, Rev: %d)\n", Get_Board_Config(), Get_Board_PCB(), Get_PLD_Version(), Get_PLD_Revision()); } @@ -245,5 +294,3 @@ void print_vcma9_info(void) { print_vcma9_rev(); } - - diff --git a/board/mpl/vcma9/vcma9.h b/board/mpl/vcma9/vcma9.h index bc0e3a4..4299d4e 100644 --- a/board/mpl/vcma9/vcma9.h +++ b/board/mpl/vcma9/vcma9.h @@ -25,11 +25,97 @@ * Global routines used for VCMA9 *****************************************************************************/ +#include <s3c2410.h> extern int mem_test(unsigned long start, unsigned long ramsize,int mode); void print_vcma9_info(void); +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +typedef enum { + NFCE_LOW, + NFCE_HIGH +} NFCE_STATE; + +static inline void NF_Conf(u16 conf) +{ + S3C2410_NAND * const nand = S3C2410_GetBase_NAND(); + + nand->NFCONF = conf; +} + +static inline void NF_Cmd(u8 cmd) +{ + S3C2410_NAND * const nand = S3C2410_GetBase_NAND(); + + nand->NFCMD = cmd; +} + +static inline void NF_CmdW(u8 cmd) +{ + NF_Cmd(cmd); + udelay(1); +} + +static inline void NF_Addr(u8 addr) +{ + S3C2410_NAND * const nand = S3C2410_GetBase_NAND(); + + nand->NFADDR = addr; +} + +static inline void NF_SetCE(NFCE_STATE s) +{ + S3C2410_NAND * const nand = S3C2410_GetBase_NAND(); + + switch (s) { + case NFCE_LOW: + nand->NFCONF &= ~(1<<11); + break; + + case NFCE_HIGH: + nand->NFCONF |= (1<<11); + break; + } +} + +static inline void NF_WaitRB(void) +{ + S3C2410_NAND * const nand = S3C2410_GetBase_NAND(); + + while (!(nand->NFSTAT & (1<<0))); +} + +static inline void NF_Write(u8 data) +{ + S3C2410_NAND * const nand = S3C2410_GetBase_NAND(); + + nand->NFDATA = data; +} + +static inline u8 NF_Read(void) +{ + S3C2410_NAND * const nand = S3C2410_GetBase_NAND(); + + return(nand->NFDATA); +} + +static inline void NF_Init_ECC(void) +{ + S3C2410_NAND * const nand = S3C2410_GetBase_NAND(); + + nand->NFCONF |= (1<<12); +} + +static inline u32 NF_Read_ECC(void) +{ + S3C2410_NAND * const nand = S3C2410_GetBase_NAND(); + + return(nand->NFECC); +} + +#endif + #define PLD_BASE_ADDRESS 0x2C000100 #define PLD_ID_REG (PLD_BASE_ADDRESS + 0) @@ -39,5 +125,3 @@ void print_vcma9_info(void); #define PLD_GPCD_REG (PLD_BASE_ADDRESS + 4) #define PLD_BOARD_REG (PLD_BASE_ADDRESS + 5) - - |