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| author | Stefan Roese <sr@denx.de> | 2009-09-24 13:59:57 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2009-09-28 10:45:54 +0200 |
| commit | 95b602bab5fec2fffab07a01ea3947c70d1bacc1 (patch) | |
| tree | acee523787d213090cc592029f1d566473bc1fd7 /board/mpl/pip405/pip405.c | |
| parent | 952e7760bfc5b0e3b142b9ce34e7fbb7d008c900 (diff) | |
| download | u-boot-imx-95b602bab5fec2fffab07a01ea3947c70d1bacc1.zip u-boot-imx-95b602bab5fec2fffab07a01ea3947c70d1bacc1.tar.gz u-boot-imx-95b602bab5fec2fffab07a01ea3947c70d1bacc1.tar.bz2 | |
ppc4xx: Convert PPC4xx SDRAM defines from lower case to upper case
The latest PPC4xx register cleanup patch missed some SDRAM defines.
This patch now changes lower case UIC defines to upper case. Also
some names are changed to match the naming in the IBM/AMCC users
manuals (e.g. mem_mcopt1 -> SDRAM0_CFG).
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/mpl/pip405/pip405.c')
| -rw-r--r-- | board/mpl/pip405/pip405.c | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c index c2d6c6f..792eccc 100644 --- a/board/mpl/pip405/pip405.c +++ b/board/mpl/pip405/pip405.c @@ -361,7 +361,7 @@ int board_early_init_f (void) SDRAM_err ("unsupported SDRAM"); /* get SDRAM timing register */ - mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); tmp = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F; /* insert CASL value */ /* tmp |= ((unsigned long)cal_val) << 23; */ @@ -385,7 +385,7 @@ int board_early_init_f (void) #endif /* write SDRAM timing register */ - mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); mtdcr (SDRAM0_CFGDATA, tmp); baseaddr = CONFIG_SYS_SDRAM_BASE; bank_size = (((unsigned long) density) << 22) / 2; @@ -418,7 +418,7 @@ int board_early_init_f (void) SDRAM_err ("unsupported SDRAM"); } /* endswitch */ /* get SDRAM bank 0 register */ - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; bank |= (baseaddr | tmp | 0x01); #ifdef SDRAM_DEBUG @@ -434,11 +434,11 @@ int board_early_init_f (void) sdram_size += bank_size; /* write SDRAM bank 0 register */ - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); mtdcr (SDRAM0_CFGDATA, bank); /* get SDRAM bank 1 register */ - mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; sdram_size = 0; @@ -459,11 +459,11 @@ int board_early_init_f (void) serial_puts ("\n"); #endif /* write SDRAM bank 1 register */ - mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); mtdcr (SDRAM0_CFGDATA, bank); /* get SDRAM bank 2 register */ - mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; bank |= (baseaddr | tmp | 0x01); @@ -482,11 +482,11 @@ int board_early_init_f (void) sdram_size += bank_size; /* write SDRAM bank 2 register */ - mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); mtdcr (SDRAM0_CFGDATA, bank); /* get SDRAM bank 3 register */ - mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; #ifdef SDRAM_DEBUG @@ -509,12 +509,12 @@ int board_early_init_f (void) #endif /* write SDRAM bank 3 register */ - mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); mtdcr (SDRAM0_CFGDATA, bank); /* get SDRAM refresh interval register */ - mtdcr (SDRAM0_CFGADDR, mem_rtr); + mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; if (tmemclk < NSto10PS (16)) @@ -523,13 +523,13 @@ int board_early_init_f (void) tmp |= 0x03F80000; /* write SDRAM refresh interval register */ - mtdcr (SDRAM0_CFGADDR, mem_rtr); + mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); mtdcr (SDRAM0_CFGDATA, tmp); /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */ - mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80E00000; - mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); mtdcr (SDRAM0_CFGDATA, tmp); @@ -619,13 +619,13 @@ phys_size_t initdram (int board_type) /* since the DRAM controller is allready set up, * calculate the size with the bank registers */ - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); bank_reg[0] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); bank_reg[1] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); bank_reg[2] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); bank_reg[3] = mfdcr (SDRAM0_CFGDATA); TotalSize = 0; for (i = 0; i < 4; i++) { |