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| author | wdenk <wdenk> | 2003-09-10 22:30:53 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2003-09-10 22:30:53 +0000 |
| commit | 7205e4075d8b50e4dd89fe39ed03860b23cbb704 (patch) | |
| tree | 0dfa865e7087ff4ee07967a2531c91ff5645a802 /board/mpl/pip405/pip405.c | |
| parent | 149dded2b178bc0fb62cb6f61b87968d914b580a (diff) | |
| download | u-boot-imx-7205e4075d8b50e4dd89fe39ed03860b23cbb704.zip u-boot-imx-7205e4075d8b50e4dd89fe39ed03860b23cbb704.tar.gz u-boot-imx-7205e4075d8b50e4dd89fe39ed03860b23cbb704.tar.bz2 | |
* Patches by Denis Peter, 9 Sep 2003:
add FAT support for IDE, SCSI and USB
* Patches by Gleb Natapov, 2 Sep 2003:
- cleanup of POST code for unsupported architectures
- MPC824x locks way0 of data cache for use as initial RAM;
this patch unlocks it after relocation to RAM and invalidates
the locked entries.
* Patch by Gleb Natapov, 30 Aug 2003:
new I2C driver for mpc107 bridge. Now works from flash.
* Patch by Dave Ellis, 11 Aug 2003:
- JFFS2: fix typo in common/cmd_jffs2.c
- JFFS2: fix CFG_JFFS2_SORT_FRAGMENTS option
- JFFS2: remove node version 0 warning
- JFFS2: accept JFFS2 PADDING nodes
- SXNI855T: add AM29LV800 support
- SXNI855T: move environment from EEPROM to flash
- SXNI855T: boot from JFFS2 in NOR or NAND flash
* Patch by Bill Hargen, 11 Aug 2003:
fixes for I2C on MPC8240
- fix i2c_write routine
- fix iprobe command
- eliminates use of global variables, plus dead code, cleanup.
Diffstat (limited to 'board/mpl/pip405/pip405.c')
| -rw-r--r-- | board/mpl/pip405/pip405.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c index a77e2c9..b4715aa 100644 --- a/board/mpl/pip405/pip405.c +++ b/board/mpl/pip405/pip405.c @@ -194,6 +194,11 @@ int board_pre_init (void) #ifdef SDRAM_DEBUG DECLARE_GLOBAL_DATA_PTR; #endif + /* set up the config port */ + mtdcr (ebccfga, pb7ap); + mtdcr (ebccfgd, CONFIG_PORT_AP); + mtdcr (ebccfga, pb7cr); + mtdcr (ebccfgd, CONFIG_PORT_CR); memclk = get_bus_freq (tmemclk); tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ @@ -657,8 +662,20 @@ static int test_dram (unsigned long ramsize) } +extern flash_info_t flash_info[]; /* info for FLASH chips */ + int misc_init_r (void) { + DECLARE_GLOBAL_DATA_PTR; + /* adjust flash start and size as well as the offset */ + gd->bd->bi_flashstart=0-flash_info[0].size; + gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN; + gd->bd->bi_flashoffset=0; + + /* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */ + if (mfdcr(strap) & PSR_ROM_LOC) + mtspr(ccr0, (mfspr(ccr0) & ~0x80)); + return (0); } |