Merge branch 'master' of /home/stefan/git/u-boot/u-boot

4 files changed, 80 insertions, 80 deletions

diff --git a/board/mpl/pati/cmd_pati.c b/board/mpl/pati/cmd_pati.c
index 98429c0..91683a3 100644
--- a/board/mpl/pati/cmd_pati.c
+++ b/board/mpl/pati/cmd_pati.c
@@ -360,12 +360,12 @@ int do_pati(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	if (strcmp(argv[1], "info") == 0)
 	{
 		show_pld_regs();
-	 	return 0;
+		return 0;
 	}
 	if (strcmp(argv[1], "pci") == 0)
 	{
 		display_pci_regs();
-	 	return 0;
+		return 0;
 	}
 	if (strcmp(argv[1], "led") == 0)
 	{
@@ -377,7 +377,7 @@ int do_pati(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		else
 			user_led1(led_on);
 		return 0;
-   	}
+	}
 #if defined(CFG_PCI_CON_DEVICE)
 	if (strcmp(argv[1], "con") == 0) {
 		pci_con_connect();
diff --git a/board/mpl/pati/pati.c b/board/mpl/pati/pati.c
index 0355b65..7893d61 100644
--- a/board/mpl/pati/pati.c
+++ b/board/mpl/pati/pati.c
@@ -484,7 +484,7 @@ int pci_con_getc(void)
 	else
 		diff=r_ptr-w_ptr;
 	if((diff<(REC_BUFFER_SIZE-4)) && buff_full) {
-   		/* clear Mail box */
+		/* clear Mail box */
 			buff_full=0;
 			PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
 	}
diff --git a/board/mpl/pati/pati.h b/board/mpl/pati/pati.h
index d521772..86c7a41 100644
--- a/board/mpl/pati/pati.h
+++ b/board/mpl/pati/pati.h
@@ -89,7 +89,7 @@
 #define SDRAM_CAL	9
 #define SDRAM_RCD	10
 #define SDRAM_WREQ	11
-#define SDRAM_PR 	12
+#define SDRAM_PR	12
 #define SDRAM_RC	13
 #define SDRAM_LMR	14
 #define SDRAM_IIP	19
@@ -128,7 +128,7 @@
 #define SDRAM_MUX0	9
 #define SDRAM_MUX1	10
 #define SDRAM_PDIS	11
-#define SDRAM_RES1 	12
+#define SDRAM_RES1	12
 #define SDRAM_RES2	13
 #define SDRAM_RES3	14
 #define SDRAM_RES4	19
@@ -177,7 +177,7 @@
 #define SDRAM_RES5	9
 #define SDRAM_CFG1	10
 #define SDRAM_CFG2	11
-#define SDRAM_CFG3 	12
+#define SDRAM_CFG3	12
 #define SDRAM_RES6	13
 #define SDRAM_CFG5	14
 #define SDRAM_CFG6	19
@@ -214,7 +214,7 @@
  * MISC Defines
  ***************************************************************/
 
-#define PCI_VENDOR_ID_MPL 	0x18E6
+#define PCI_VENDOR_ID_MPL	0x18E6
 #define PCI_DEVICE_ID_PATI	0x00DA
 
 #if defined(CONFIG_MIP405)
@@ -269,12 +269,12 @@
 
 /* Config Area */
 #define PATI_LOC_CFG_ADDR		0x07000000		/* Local Address */
-#define PATI_LOC_CFG_MASK		0xFFFFFF00  		/* 256 Bytes */
+#define PATI_LOC_CFG_MASK		0xFFFFFF00		/* 256 Bytes */
 /* Attributes */
-#define PATI_LOC_CFG_BUS_SIZE		PATI_BUS_SIZE_32  	/* 32 Bit */
-#define PATI_LOC_CFG_BURST		0  			/* No Burst */
-#define PATI_LOC_CFG_NO_PREFETCH	1  			/* No Prefetch */
-#define PATI_LOC_CFG_TA_ENABLE		1 			/* Enable TA */
+#define PATI_LOC_CFG_BUS_SIZE		PATI_BUS_SIZE_32	/* 32 Bit */
+#define PATI_LOC_CFG_BURST		0			/* No Burst */
+#define PATI_LOC_CFG_NO_PREFETCH	1			/* No Prefetch */
+#define PATI_LOC_CFG_TA_ENABLE		1			/* Enable TA */
 
 #define PATI_LOC_CFG_SPACE0_ATTR  ( \
 		PATI_LOC_CFG_BUS_SIZE | \
@@ -295,10 +295,10 @@
 #define PATI_LOC_SDRAM_ADDR		0x06000000		/* Local Address */
 #define PATI_LOC_SDRAM_MASK		0xFFF00000		/* 1MByte */
 /* Attributes */
-#define PATI_LOC_SDRAM_BUS_SIZE		PATI_BUS_SIZE_32  	/* 32 Bit */
-#define PATI_LOC_SDRAM_BURST		0  			/* No Burst */
-#define PATI_LOC_SDRAM_NO_PREFETCH	0  			/* Prefetch */
-#define PATI_LOC_SDRAM_TA_ENABLE	1  			/* Enable TA */
+#define PATI_LOC_SDRAM_BUS_SIZE		PATI_BUS_SIZE_32	/* 32 Bit */
+#define PATI_LOC_SDRAM_BURST		0			/* No Burst */
+#define PATI_LOC_SDRAM_NO_PREFETCH	0			/* Prefetch */
+#define PATI_LOC_SDRAM_TA_ENABLE	1			/* Enable TA */
 
 /* should never be used */
 #define PATI_LOC_SDRAM_SPACE0_ATTR  ( \
@@ -319,10 +319,10 @@
 #define PATI_LOC_FLASH_ADDR		0x03000000		/* Local Address */
 #define PATI_LOC_FLASH_MASK		0xFFF00000		/* 1MByte */
 /* Attributes */
-#define PATI_LOC_FLASH_BUS_SIZE		PATI_BUS_SIZE_16  	/* 16 Bit */
-#define PATI_LOC_FLASH_BURST		0  			/* No Burst */
-#define PATI_LOC_FLASH_NO_PREFETCH	1  			/* No Prefetch */
-#define PATI_LOC_FLASH_TA_ENABLE	1  			/* Enable TA */
+#define PATI_LOC_FLASH_BUS_SIZE		PATI_BUS_SIZE_16	/* 16 Bit */
+#define PATI_LOC_FLASH_BURST		0			/* No Burst */
+#define PATI_LOC_FLASH_NO_PREFETCH	1			/* No Prefetch */
+#define PATI_LOC_FLASH_TA_ENABLE	1			/* Enable TA */
 
 /* should never be used */
 #define PATI_LOC_FLASH_SPACE0_ATTR  ( \
@@ -343,7 +343,7 @@
 #define PATI_LOC_CPU_ADDR		0x01000000		/* Local Address */
 #define PATI_LOC_CPU_MASK		0xFFF00000		/* 1Mbyte */
 /* Attributes */
-#define PATI_LOC_CPU_BUS_SIZE		PATI_BUS_SIZE_32  	/* 32 Bit */
+#define PATI_LOC_CPU_BUS_SIZE		PATI_BUS_SIZE_32	/* 32 Bit */
 #define PATI_LOC_CPU_BURST		0			/* No Burst */
 #define PATI_LOC_CPU_NO_PREFETCH	1			/* No Prefetch */
 #define PATI_LOC_CPU_TA_ENABLE		1			/* Enable TA */
@@ -393,9 +393,9 @@
 
 
 #define PATI_HW_START		((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF))
-#define PATI_HW_PCI_ONLY 	((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY))
+#define PATI_HW_PCI_ONLY	((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY))
 #define PATI_HW_CPU_ACC		((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY))
-#define PATI_HW_CPU_SLAVE 	((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY | LOCAL_CPU_SLAVE))
+#define PATI_HW_CPU_SLAVE	((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY | LOCAL_CPU_SLAVE))
 
 /***************************************************
  * Direct Master Config
@@ -404,12 +404,12 @@
 #define PATI_BUS_MASTER 1
 
 
-#define PATI_DMASTER_MASK 		0xFFF00000  /* 1MByte */
-#define PATI_DMASTER_ADDR 		0x01000000  /* Local Address */
+#define PATI_DMASTER_MASK		0xFFF00000  /* 1MByte */
+#define PATI_DMASTER_ADDR		0x01000000  /* Local Address */
 
-#define PATI_DMASTER_MEMORY_EN 		0x00000001 /* 0x00000001 */
-#define PATI_DMASTER_READ_AHEAD 	0x00000004 /* 0x00000004 */
-#define PATI_DMASTER_READ_NOT_AHEAD 	0x00000000 /* 0x00000004 */
+#define PATI_DMASTER_MEMORY_EN		0x00000001 /* 0x00000001 */
+#define PATI_DMASTER_READ_AHEAD		0x00000004 /* 0x00000004 */
+#define PATI_DMASTER_READ_NOT_AHEAD	0x00000000 /* 0x00000004 */
 #define PATI_DMASTER_PRE_SIZE_CNTRL_0	0x00000000
 #define PATI_DMASTER_PRE_SIZE_CNTRL_4	0x00000008
 #define PATI_DMASTER_PRE_SIZE_CNTRL_8	0x00001000
diff --git a/board/mpl/pati/pci_eeprom.h b/board/mpl/pati/pci_eeprom.h
index 9658808..af34b86 100644
--- a/board/mpl/pati/pci_eeprom.h
+++ b/board/mpl/pati/pci_eeprom.h
@@ -35,57 +35,57 @@ typedef struct pci_eeprom_t {
 } pci_eeprom;
 
 static pci_eeprom pati_eeprom[] = {
-	{ 0x00,PCI_DEVICE_ID_PATI }, 	/* PCI Device ID PCIIDR[31:16] */
-	{ 0x02,PCI_VENDOR_ID_MPL }, 	/* PCI Vendor ID PCIIDR[15:0] */
-	{ 0x04,PCI_CLASS_PROCESSOR_POWERPC }, 	/* PCI Class Code PCICCR[23:8] */
-	{ 0x06,0x00BA }, 	/* PCI Class Code / PCI Revision ID PCICCR[7:0] / PCIREV[7:0] */
-	{ 0x08,0x0007 }, 	/* PCI Maximum Latency / PCI Minimum Grant PCIMLR[7:0] / PCIMGR[7:0] */
-	{ 0x0A,0x0100 }, 	/* PCI Interrupt Pin / PCI Interrupt Line PCIIPR[7:0] / PCIILR[7:0] */
-	{ 0x0C,0x0000 }, 	/* MSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[31:16] */
-	{ 0x0E,0x0000 }, 	/* LSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[15:0] */
-	{ 0x10,0x0000 }, 	/* MSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[31:16] */
-	{ 0x12,0x0000 }, 	/* LSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[15:0] */
-	{ 0x14,HIGH_WORD(PATI_LOC_CFG_MASK) }, 	/* MSW of Direct Slave Local Address Space 0 Range LAS0RR[31:16] */
-	{ 0x16,LOW_WORD(PATI_LOC_CFG_MASK) }, 	/* LSW of Direct Slave Local Address Space 0 Range LAS0RR[15:0] */
-	{ 0x18,HIGH_WORD(PATI_LOC_CFG_ADDR) }, 	/* MSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[31:16] (CFG) */
-	{ 0x1A,LOW_WORD(PATI_LOC_CFG_ADDR)|1 }, 	/* LSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[15:2, 0], Reserved [1] */
-	{ 0x1C,0x0000 }, 	/* MSW of Mode/DMA Arbitration MARBR[31, 29:16] or DMAARB[31, 29:16], Reserved [30] */
-	{ 0x1E,0x0000 }, 	/* LSW of Mode/DMA Arbitration MARBR[15:0] or DMAARB[15:0] */
-	{ 0x20,0x0030 }, 	/* Local Miscellaneous Control 2 / Serial EEPROM WP Addr Boundary LMISC2[5:0], Res[7:6] / PROT_AREA[6:0], Res[7] */
-	{ 0x22,0x0510 }, 	/* Local Miscellaneous Control 1 / Local Bus Big/Little Endian Descriptor LMISC1[7:0] / BIGEND[7:0] */
-	{ 0x24,0x0000 }, 	/* MSW of Direct Slave Expansion ROM Range EROMRR[31:16] */
-	{ 0x26,0x0000 }, 	/* LSW of Direct Slave Expansion ROM Range EROMRR[15:11, 0], Reserved [10:1]  */
-	{ 0x28,0x0000 }, 	/* MSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[31:16] */
-	{ 0x2A,0x0000 }, 	/* LSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[15:11, 5:0], Reserved [10:6] */
-	{ 0x2C,(0x4243 | HIGH_WORD((PATI_LOC_CFG_SPACE0_ATTR))) }, 	/* MSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[31:16] */
-	{ 0x2E,LOW_WORD(PATI_LOC_CFG_SPACE0_ATTR) }, 	/* LSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[15:0] */
-	{ 0x30,HIGH_WORD(PATI_DMASTER_MASK) }, 	/* MSW of Local Range for Direct Master-to-PCI DMRR[31:16] */
-	{ 0x32,LOW_WORD(PATI_DMASTER_MASK) }, 	/* LSW of Local Range for Direct Master-to-PCI (Reserved) DMRR[15:0] */
-	{ 0x34,HIGH_WORD(PATI_DMASTER_ADDR) }, 	/* MSW of Local Base Address for Direct Master-to-PCI Memory DMLBAM[31:16] */
-	{ 0x36,LOW_WORD(PATI_DMASTER_ADDR) }, 	/* LSW of Local Base Address for Direct Master-to-PCI Memory (Reserved) DMLBAM[15:0] */
-	{ 0x38,0x0000 }, 	/* MSW of Local Bus Address for Direct Master-to-PCI I/O Configuration DMLBAI[31:16] */
-	{ 0x3A,0x0000 }, 	/* LSW of Local Bus Address for Direct Master-to-PCI I/O Configuration (Reserved) DMLBAI[15:0] */
-	{ 0x3C,0x0000 }, 	/* MSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[31:16] */
-	{ 0x3E,0x0000 }, 	/* LSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[15:0] */
-	{ 0x40,0x0000 }, 	/* MSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[31, 23:16] Reserved [30:24]*/
-	{ 0x42,0x0000 }, 	/* LSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[15:0] */
-	{ 0x44,0x0000 }, 	/* PCI Subsystem ID PCISID[15:0] */
-	{ 0x46,0x0000 }, 	/* PCI Subsystem Vendor ID PCISVID[15:0] */
-	{ 0x48,HIGH_WORD(PATI_LOC_SDRAM_MASK) }, 	/* MSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[31:16] */
-	{ 0x4A,LOW_WORD(PATI_LOC_SDRAM_MASK) }, 	/* LSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[15:0] */
-	{ 0x4C,HIGH_WORD(PATI_LOC_SDRAM_ADDR) }, 	/* MSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[31:16] (SDRAM) */
-	{ 0x4E,LOW_WORD(PATI_LOC_SDRAM_ADDR) | 0x1 }, 	/* LSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[15:2, 0], Reserved [1] */
-	{ 0x50,HIGH_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) }, 	/* MSW of Local Address Space 1 Bus Region Descriptor LBRD1[31:16] */
-	{ 0x52,LOW_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) }, 	/* LSW of Local Address Space 1 Bus Region Descriptor (Reserved) LBRD1[15:0] */
-	{ 0x54,0x0000 }, 	/* Hot Swap Control/Status (Reserved) Reserved */
-	{ 0x56,0x0000 }, 	/* Hot Swap Next Capability Pointer / Hot Swap Control HS_NEXT[7:0] / HS_CNTL[7:0] */
-	{ 0x58,0x0000 }, 	/* Reserved Reserved */
-	{ 0x5A,0x0000 }, 	/* PCI Arbiter Control PCIARB[3:0], Reserved [15:4] */
-	{ 0x5C,0x0000 }, 	/* Power Management Capabilities PMC[15:9, 2:0] */
-	{ 0x5E,0x0000 }, 	/* Power Management Next Capability Pointer (Reserved) / Power Management Capability ID (Reserved) Reserved*/
-	{ 0x60,0x0000 }, 	/* Power Management Data / PMCSR Bridge Support Extension (Reserved) PMDATA[7:0] / Reserved */
-	{ 0x62,0x0000 }, 	/* Power Management Control/Status PMCSR[14:8] */
-	{ 0xFFFF,0xFFFF} 	/* terminaror */
+	{ 0x00,PCI_DEVICE_ID_PATI },	/* PCI Device ID PCIIDR[31:16] */
+	{ 0x02,PCI_VENDOR_ID_MPL },	/* PCI Vendor ID PCIIDR[15:0] */
+	{ 0x04,PCI_CLASS_PROCESSOR_POWERPC },	/* PCI Class Code PCICCR[23:8] */
+	{ 0x06,0x00BA },	/* PCI Class Code / PCI Revision ID PCICCR[7:0] / PCIREV[7:0] */
+	{ 0x08,0x0007 },	/* PCI Maximum Latency / PCI Minimum Grant PCIMLR[7:0] / PCIMGR[7:0] */
+	{ 0x0A,0x0100 },	/* PCI Interrupt Pin / PCI Interrupt Line PCIIPR[7:0] / PCIILR[7:0] */
+	{ 0x0C,0x0000 },	/* MSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[31:16] */
+	{ 0x0E,0x0000 },	/* LSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[15:0] */
+	{ 0x10,0x0000 },	/* MSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[31:16] */
+	{ 0x12,0x0000 },	/* LSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[15:0] */
+	{ 0x14,HIGH_WORD(PATI_LOC_CFG_MASK) },	/* MSW of Direct Slave Local Address Space 0 Range LAS0RR[31:16] */
+	{ 0x16,LOW_WORD(PATI_LOC_CFG_MASK) },	/* LSW of Direct Slave Local Address Space 0 Range LAS0RR[15:0] */
+	{ 0x18,HIGH_WORD(PATI_LOC_CFG_ADDR) },	/* MSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[31:16] (CFG) */
+	{ 0x1A,LOW_WORD(PATI_LOC_CFG_ADDR)|1 },	/* LSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[15:2, 0], Reserved [1] */
+	{ 0x1C,0x0000 },	/* MSW of Mode/DMA Arbitration MARBR[31, 29:16] or DMAARB[31, 29:16], Reserved [30] */
+	{ 0x1E,0x0000 },	/* LSW of Mode/DMA Arbitration MARBR[15:0] or DMAARB[15:0] */
+	{ 0x20,0x0030 },	/* Local Miscellaneous Control 2 / Serial EEPROM WP Addr Boundary LMISC2[5:0], Res[7:6] / PROT_AREA[6:0], Res[7] */
+	{ 0x22,0x0510 },	/* Local Miscellaneous Control 1 / Local Bus Big/Little Endian Descriptor LMISC1[7:0] / BIGEND[7:0] */
+	{ 0x24,0x0000 },	/* MSW of Direct Slave Expansion ROM Range EROMRR[31:16] */
+	{ 0x26,0x0000 },	/* LSW of Direct Slave Expansion ROM Range EROMRR[15:11, 0], Reserved [10:1]  */
+	{ 0x28,0x0000 },	/* MSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[31:16] */
+	{ 0x2A,0x0000 },	/* LSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[15:11, 5:0], Reserved [10:6] */
+	{ 0x2C,(0x4243 | HIGH_WORD((PATI_LOC_CFG_SPACE0_ATTR))) },	/* MSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[31:16] */
+	{ 0x2E,LOW_WORD(PATI_LOC_CFG_SPACE0_ATTR) },	/* LSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[15:0] */
+	{ 0x30,HIGH_WORD(PATI_DMASTER_MASK) },	/* MSW of Local Range for Direct Master-to-PCI DMRR[31:16] */
+	{ 0x32,LOW_WORD(PATI_DMASTER_MASK) },	/* LSW of Local Range for Direct Master-to-PCI (Reserved) DMRR[15:0] */
+	{ 0x34,HIGH_WORD(PATI_DMASTER_ADDR) },	/* MSW of Local Base Address for Direct Master-to-PCI Memory DMLBAM[31:16] */
+	{ 0x36,LOW_WORD(PATI_DMASTER_ADDR) },	/* LSW of Local Base Address for Direct Master-to-PCI Memory (Reserved) DMLBAM[15:0] */
+	{ 0x38,0x0000 },	/* MSW of Local Bus Address for Direct Master-to-PCI I/O Configuration DMLBAI[31:16] */
+	{ 0x3A,0x0000 },	/* LSW of Local Bus Address for Direct Master-to-PCI I/O Configuration (Reserved) DMLBAI[15:0] */
+	{ 0x3C,0x0000 },	/* MSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[31:16] */
+	{ 0x3E,0x0000 },	/* LSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[15:0] */
+	{ 0x40,0x0000 },	/* MSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[31, 23:16] Reserved [30:24]*/
+	{ 0x42,0x0000 },	/* LSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[15:0] */
+	{ 0x44,0x0000 },	/* PCI Subsystem ID PCISID[15:0] */
+	{ 0x46,0x0000 },	/* PCI Subsystem Vendor ID PCISVID[15:0] */
+	{ 0x48,HIGH_WORD(PATI_LOC_SDRAM_MASK) },	/* MSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[31:16] */
+	{ 0x4A,LOW_WORD(PATI_LOC_SDRAM_MASK) },	/* LSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[15:0] */
+	{ 0x4C,HIGH_WORD(PATI_LOC_SDRAM_ADDR) },	/* MSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[31:16] (SDRAM) */
+	{ 0x4E,LOW_WORD(PATI_LOC_SDRAM_ADDR) | 0x1 },	/* LSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[15:2, 0], Reserved [1] */
+	{ 0x50,HIGH_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) },	/* MSW of Local Address Space 1 Bus Region Descriptor LBRD1[31:16] */
+	{ 0x52,LOW_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) },	/* LSW of Local Address Space 1 Bus Region Descriptor (Reserved) LBRD1[15:0] */
+	{ 0x54,0x0000 },	/* Hot Swap Control/Status (Reserved) Reserved */
+	{ 0x56,0x0000 },	/* Hot Swap Next Capability Pointer / Hot Swap Control HS_NEXT[7:0] / HS_CNTL[7:0] */
+	{ 0x58,0x0000 },	/* Reserved Reserved */
+	{ 0x5A,0x0000 },	/* PCI Arbiter Control PCIARB[3:0], Reserved [15:4] */
+	{ 0x5C,0x0000 },	/* Power Management Capabilities PMC[15:9, 2:0] */
+	{ 0x5E,0x0000 },	/* Power Management Next Capability Pointer (Reserved) / Power Management Capability ID (Reserved) Reserved*/
+	{ 0x60,0x0000 },	/* Power Management Data / PMCSR Bridge Support Extension (Reserved) PMDATA[7:0] / Reserved */
+	{ 0x62,0x0000 },	/* Power Management Control/Status PMCSR[14:8] */
+	{ 0xFFFF,0xFFFF}	/* terminaror */
 };
 #define PATI_EEPROM_LAST_OFFSET	0x64
 #endif /* #ifndef __PCI_EEPROM_H_ */