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| author | wdenk <wdenk> | 2003-09-10 22:30:53 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2003-09-10 22:30:53 +0000 |
| commit | 7205e4075d8b50e4dd89fe39ed03860b23cbb704 (patch) | |
| tree | 0dfa865e7087ff4ee07967a2531c91ff5645a802 /board/mpl/mip405/mip405.h | |
| parent | 149dded2b178bc0fb62cb6f61b87968d914b580a (diff) | |
| download | u-boot-imx-7205e4075d8b50e4dd89fe39ed03860b23cbb704.zip u-boot-imx-7205e4075d8b50e4dd89fe39ed03860b23cbb704.tar.gz u-boot-imx-7205e4075d8b50e4dd89fe39ed03860b23cbb704.tar.bz2 | |
* Patches by Denis Peter, 9 Sep 2003:
add FAT support for IDE, SCSI and USB
* Patches by Gleb Natapov, 2 Sep 2003:
- cleanup of POST code for unsupported architectures
- MPC824x locks way0 of data cache for use as initial RAM;
this patch unlocks it after relocation to RAM and invalidates
the locked entries.
* Patch by Gleb Natapov, 30 Aug 2003:
new I2C driver for mpc107 bridge. Now works from flash.
* Patch by Dave Ellis, 11 Aug 2003:
- JFFS2: fix typo in common/cmd_jffs2.c
- JFFS2: fix CFG_JFFS2_SORT_FRAGMENTS option
- JFFS2: remove node version 0 warning
- JFFS2: accept JFFS2 PADDING nodes
- SXNI855T: add AM29LV800 support
- SXNI855T: move environment from EEPROM to flash
- SXNI855T: boot from JFFS2 in NOR or NAND flash
* Patch by Bill Hargen, 11 Aug 2003:
fixes for I2C on MPC8240
- fix i2c_write routine
- fix iprobe command
- eliminates use of global variables, plus dead code, cleanup.
Diffstat (limited to 'board/mpl/mip405/mip405.h')
| -rw-r--r-- | board/mpl/mip405/mip405.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/board/mpl/mip405/mip405.h b/board/mpl/mip405/mip405.h index f1e37ff..b1d91de 100644 --- a/board/mpl/mip405/mip405.h +++ b/board/mpl/mip405/mip405.h @@ -137,13 +137,13 @@ void user_led0(unsigned char on); (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5)) /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ -#define FLASH_BS 2 /* 4 MByte */ +#define FLASH_BS FLASH_SIZE_PRELIM /* 4 MByte */ /* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ #define FLASH_BU 3 /* R/W */ /* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ #define FLASH_BW 1 /* 16Bit */ /* CR register for Boot */ -#define FLASH_CR_B ((FLASH_BASE0_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13)) +#define FLASH_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13)) /* CR register for non Boot */ #define FLASH_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13)) @@ -172,11 +172,12 @@ void user_led0(unsigned char on); /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ #define MPS_BS 2 /* 4 MByte */ +#define MPS_BS_B FLASH_SIZE_PRELIM /* 1 MByte */ /* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ #define MPS_BU 3 /* R/W */ /* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ #define MPS_BW 0 /* 8Bit */ /* CR register for Boot */ -#define MPS_CR_B ((FLASH_BASE0_PRELIM & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13)) +#define MPS_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS_B << 17) + (MPS_BU << 15) + (MPS_BW << 13)) /* CR register for non Boot */ #define MPS_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13)) |