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| author | Wolfgang Denk <wd@denx.de> | 2009-09-15 21:43:25 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2009-09-15 21:43:25 +0200 |
| commit | cae26e2fdd9934644086fda9f7cbc336a1fe5ce8 (patch) | |
| tree | 5f9ae145135d5583fadff9564196fbf5f10e34ea /board/mpl/mip405/init.S | |
| parent | 6c7bc91fb3dba186d3398a1653f6db236510ffa7 (diff) | |
| parent | 4c1883670acbf1cc83c04df1876235c3aedde128 (diff) | |
| download | u-boot-imx-cae26e2fdd9934644086fda9f7cbc336a1fe5ce8.zip u-boot-imx-cae26e2fdd9934644086fda9f7cbc336a1fe5ce8.tar.gz u-boot-imx-cae26e2fdd9934644086fda9f7cbc336a1fe5ce8.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
Diffstat (limited to 'board/mpl/mip405/init.S')
| -rw-r--r-- | board/mpl/mip405/init.S | 74 |
1 files changed, 37 insertions, 37 deletions
diff --git a/board/mpl/mip405/init.S b/board/mpl/mip405/init.S index 19d9220..f3d94c3 100644 --- a/board/mpl/mip405/init.S +++ b/board/mpl/mip405/init.S @@ -55,7 +55,7 @@ .globl ext_bus_cntlr_init ext_bus_cntlr_init: mflr r4 /* save link register */ - mfdcr r3,strap /* get strapping reg */ + mfdcr r3,CPC0_PSR /* get strapping reg */ andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */ bnelr /* jump back if PCI boot */ @@ -84,9 +84,9 @@ ext_bus_cntlr_init: /*----------------------------------------------------------------------- * decide boot up mode *----------------------------------------------------------------------- */ - addi r4,0,pb0cr - mtdcr ebccfga,r4 - mfdcr r4,ebccfgd + addi r4,0,PB0CR + mtdcr EBC0_CFGADDR,r4 + mfdcr r4,EBC0_CFGDATA andi. r0, r4, 0x2000 /* mask out irrelevant bits */ beq 0f /* jump if 8 bit bus width */ @@ -96,18 +96,18 @@ ext_bus_cntlr_init: * Memory Bank 0 (16 Bit Flash) initialization *---------------------------------------------------------------------- */ - addi r4,0,pb0ap - mtdcr ebccfga,r4 + addi r4,0,PB1AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,(FLASH_AP_B)@h ori r4,r4,(FLASH_AP_B)@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb0cr - mtdcr ebccfga,r4 + addi r4,0,PB0CR + mtdcr EBC0_CFGADDR,r4 /* BS=0x010(4MB),BU=0x3(R/W), */ addis r4,0,(FLASH_CR_B)@h ori r4,r4,(FLASH_CR_B)@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 b 1f 0: @@ -117,66 +117,66 @@ ext_bus_cntlr_init: * Memory Bank 0 Multi Purpose Socket initialization *----------------------------------------------------------------------- */ /* 0x7F8FFE80 slowest boot */ - addi r4,0,pb0ap - mtdcr ebccfga,r4 + addi r4,0,PB1AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,(MPS_AP_B)@h ori r4,r4,(MPS_AP_B)@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb0cr - mtdcr ebccfga,r4 + addi r4,0,PB0CR + mtdcr EBC0_CFGADDR,r4 /* BS=0x010(4MB),BU=0x3(R/W), */ addis r4,0,(MPS_CR_B)@h ori r4,r4,(MPS_CR_B)@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 1: /*----------------------------------------------------------------------- * Memory Bank 2-3-4-5-6 (not used) initialization *-----------------------------------------------------------------------*/ - addi r4,0,pb1cr - mtdcr ebccfga,r4 + addi r4,0,PB1CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb2cr - mtdcr ebccfga,r4 + addi r4,0,PB2CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb3cr - mtdcr ebccfga,r4 + addi r4,0,PB3CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb4cr - mtdcr ebccfga,r4 + addi r4,0,PB4CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb5cr - mtdcr ebccfga,r4 + addi r4,0,PB5CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb6cr - mtdcr ebccfga,r4 + addi r4,0,PB6CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb7cr - mtdcr ebccfga,r4 + addi r4,0,PB7CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 nop /* pass2 DCR errata #8 */ blr |