summaryrefslogtreecommitdiff
path: root/board/mpl/mip405/init.S
diff options
context:
space:
mode:
authorwdenk <wdenk>2003-09-10 22:30:53 +0000
committerwdenk <wdenk>2003-09-10 22:30:53 +0000
commit7205e4075d8b50e4dd89fe39ed03860b23cbb704 (patch)
tree0dfa865e7087ff4ee07967a2531c91ff5645a802 /board/mpl/mip405/init.S
parent149dded2b178bc0fb62cb6f61b87968d914b580a (diff)
downloadu-boot-imx-7205e4075d8b50e4dd89fe39ed03860b23cbb704.zip
u-boot-imx-7205e4075d8b50e4dd89fe39ed03860b23cbb704.tar.gz
u-boot-imx-7205e4075d8b50e4dd89fe39ed03860b23cbb704.tar.bz2
* Patches by Denis Peter, 9 Sep 2003:
add FAT support for IDE, SCSI and USB * Patches by Gleb Natapov, 2 Sep 2003: - cleanup of POST code for unsupported architectures - MPC824x locks way0 of data cache for use as initial RAM; this patch unlocks it after relocation to RAM and invalidates the locked entries. * Patch by Gleb Natapov, 30 Aug 2003: new I2C driver for mpc107 bridge. Now works from flash. * Patch by Dave Ellis, 11 Aug 2003: - JFFS2: fix typo in common/cmd_jffs2.c - JFFS2: fix CFG_JFFS2_SORT_FRAGMENTS option - JFFS2: remove node version 0 warning - JFFS2: accept JFFS2 PADDING nodes - SXNI855T: add AM29LV800 support - SXNI855T: move environment from EEPROM to flash - SXNI855T: boot from JFFS2 in NOR or NAND flash * Patch by Bill Hargen, 11 Aug 2003: fixes for I2C on MPC8240 - fix i2c_write routine - fix iprobe command - eliminates use of global variables, plus dead code, cleanup.
Diffstat (limited to 'board/mpl/mip405/init.S')
-rw-r--r--board/mpl/mip405/init.S24
1 files changed, 5 insertions, 19 deletions
diff --git a/board/mpl/mip405/init.S b/board/mpl/mip405/init.S
index 00bf739..3351b5b 100644
--- a/board/mpl/mip405/init.S
+++ b/board/mpl/mip405/init.S
@@ -87,19 +87,15 @@ ext_bus_cntlr_init:
mfdcr r4,ebccfgd
andi. r0, r4, 0x2000 /* mask out irrelevant bits */
- beq 0f /* jump if 8 bit bus width */
+ beq 0f /* jump if 8 bit bus width */
- /* setup 16 bit things (Flash Boot)
+ /* setup 16 bit things
*-----------------------------------------------------------------------
* Memory Bank 0 (16 Bit Flash) initialization
*---------------------------------------------------------------------- */
addi r4,0,pb0ap
mtdcr ebccfga,r4
-/* addis r4,0,0xFF8F */
-/* ori r4,r4,0xFE80 */
-/* addis r4,0,0x9B01 */
-/* ori r4,r4,0x5480 */
addis r4,0,(FLASH_AP_B)@h
ori r4,r4,(FLASH_AP_B)@l
mtdcr ebccfgd,r4
@@ -107,8 +103,6 @@ ext_bus_cntlr_init:
addi r4,0,pb0cr
mtdcr ebccfga,r4
/* BS=0x010(4MB),BU=0x3(R/W), */
-/* addis r4,0,((FLASH_BASE0_PRELIM & 0xFFF00000) | 0x00050000)@h */
-/* ori r4,r4,0xA000 / * BW=0x01(16 bits) */
addis r4,0,(FLASH_CR_B)@h
ori r4,r4,(FLASH_CR_B)@l
mtdcr ebccfgd,r4
@@ -123,21 +117,13 @@ ext_bus_cntlr_init:
/* 0x7F8FFE80 slowest boot */
addi r4,0,pb0ap
mtdcr ebccfga,r4
-#if 0
- addis r4,0,0x9B01
- ori r4,r4,0x5480
-#else
addis r4,0,(MPS_AP_B)@h
ori r4,r4,(MPS_AP_B)@l
-#endif
mtdcr ebccfgd,r4
addi r4,0,pb0cr
mtdcr ebccfga,r4
/* BS=0x010(4MB),BU=0x3(R/W), */
-/* addis r4,0,((FLASH_BASE0_PRELIM & 0xFFF00000) | 0x00050000)@h */
-/* ori r4,r4,0x8000 / * BW=0x0( 8 bits) */
-
addis r4,0,(MPS_CR_B)@h
ori r4,r4,(MPS_CR_B)@l
@@ -178,18 +164,18 @@ ext_bus_cntlr_init:
ori r4,r4,0x0000
mtdcr ebccfgd,r4
- addi r4,0,pb6cr
+ addi r4,0,pb6cr
mtdcr ebccfga,r4
addis r4,0,0x0000
ori r4,r4,0x0000
mtdcr ebccfgd,r4
- addi r4,0,pb7cr
+ addi r4,0,pb7cr
mtdcr ebccfga,r4
addis r4,0,0x0000
ori r4,r4,0x0000
mtdcr ebccfgd,r4
- nop /* pass2 DCR errata #8 */
+ nop /* pass2 DCR errata #8 */
blr
/*-----------------------------------------------------------------------------