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authorwdenk <wdenk>2003-06-04 15:05:30 +0000
committerwdenk <wdenk>2003-06-04 15:05:30 +0000
commitf3e0de60a6dfa2bedd99bda257841a22b5153f42 (patch)
tree0dde9b4b5335d5889587fc19f7870db1034b636e /board/mpl/common/pci_parts.h
parent682011ff6968198da14b89e40d9f55b00f6d91f7 (diff)
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* Patch by Denis Peter, 04 June 2003:
add support for the MIP405T board
Diffstat (limited to 'board/mpl/common/pci_parts.h')
-rw-r--r--board/mpl/common/pci_parts.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/board/mpl/common/pci_parts.h b/board/mpl/common/pci_parts.h
index 944585f..a8e3232 100644
--- a/board/mpl/common/pci_parts.h
+++ b/board/mpl/common/pci_parts.h
@@ -108,17 +108,23 @@ static struct pci_pip405_config_entry piix4_isa_bridge_f0[] = {
/* PIIX4 IDE Controller Function 1 */
static struct pci_pip405_config_entry piix4_ide_cntrl_f1[] = {
{PCI_COMMAND, 0x0001, 2}, /* enable IO access */
+#if !defined(CONFIG_MIP405T)
{PCI_CFG_PIIX4_IDETIM, 0x80008000, 4}, /* enable Both IDE channels */
+#else
+ {PCI_CFG_PIIX4_IDETIM, 0x80000000, 4}, /* enable IDE channel0 */
+#endif
{ } /* end of device table */
};
/* PIIX4 USB Controller Function 2 */
static struct pci_pip405_config_entry piix4_usb_cntrl_f2[] = {
+#if !defined(CONFIG_MIP405T)
{PCI_INTERRUPT_LINE, 31, 1}, /* Int vector = 31 */
{PCI_BASE_ADDRESS_4, 0x0000E001, 4}, /* Set IO Address to 0xe000 to 0xe01F */
{PCI_LATENCY_TIMER, 0x80, 1}, /* Latency Timer 0x80 */
{0xC0, 0x2000, 2}, /* Legacy support */
{PCI_COMMAND, 0x0005, 2}, /* enable IO access and Master */
+#endif
{ } /* end of device table */
};