Merge git://www.denx.de/git/u-boot

1 files changed, 3 insertions, 110 deletions

diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c
index b2cf4a9..7d7e2af 100644
--- a/board/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/mpc8641hpcn/mpc8641hpcn.c
@@ -1,9 +1,5 @@
 /*
- * Copyright 2004 Freescale Semiconductor.
- * Jeff Brown
- * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ * Copyright 2006, 2007 Freescale Semiconductor.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -25,18 +21,18 @@
  */
 
 #include <common.h>
-#include <command.h>
 #include <pci.h>
 #include <asm/processor.h>
 #include <asm/immap_86xx.h>
 #include <spd.h>
+#include <asm/io.h>
 
 #if defined(CONFIG_OF_FLAT_TREE)
 #include <ft_build.h>
 extern void ft_cpu_setup(void *blob, bd_t *bd);
 #endif
 
-#include "pixis.h"
+#include "../freescale/common/pixis.h"
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
@@ -258,109 +254,6 @@ ft_board_setup(void *blob, bd_t *bd)
 #endif
 
 
-void
-mpc8641_reset_board(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
-{
-	char cmd;
-	ulong val;
-	ulong corepll;
-
-	/*
-	 * No args is a simple reset request.
-	 */
-	if (argc <= 1) {
-		out8(PIXIS_BASE + PIXIS_RST, 0);
-		/* not reached */
-	}
-
-	cmd = argv[1][1];
-	switch (cmd) {
-	case 'f':		/* reset with frequency changed */
-		if (argc < 5)
-			goto my_usage;
-		read_from_px_regs(0);
-
-		val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
-
-		corepll = strfractoint(argv[3]);
-		val = val + set_px_corepll(corepll);
-		val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
-		if (val == 3) {
-			puts("Setting registers VCFGEN0 and VCTL\n");
-			read_from_px_regs(1);
-			puts("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n");
-			set_px_go();
-		} else
-			goto my_usage;
-
-		while (1) ;	/* Not reached */
-
-	case 'l':
-		if (argv[2][1] == 'f') {
-			read_from_px_regs(0);
-			read_from_px_regs_altbank(0);
-			/* reset with frequency changed */
-			val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
-
-			corepll = strfractoint(argv[4]);
-			val = val + set_px_corepll(corepll);
-			val = val + set_px_mpxpll(simple_strtoul(argv[5],
-								 NULL, 10));
-			if (val == 3) {
-				puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
-				set_altbank();
-				read_from_px_regs(1);
-				read_from_px_regs_altbank(1);
-				puts("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n");
-				set_px_go_with_watchdog();
-			} else
-				goto my_usage;
-
-			while (1) ;	/* Not reached */
-
-		} else if (argv[2][1] == 'd') {
-			/*
-			 * Reset from alternate bank without changing
-			 * frequencies but with watchdog timer enabled.
-			 */
-			read_from_px_regs(0);
-			read_from_px_regs_altbank(0);
-			puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
-			set_altbank();
-			read_from_px_regs_altbank(1);
-			puts("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
-			set_px_go_with_watchdog();
-			while (1) ;	/* Not reached */
-
-		} else {
-			/*
-			 * Reset from next bank without changing
-			 * frequency and without watchdog timer enabled.
-			 */
-			read_from_px_regs(0);
-			read_from_px_regs_altbank(0);
-			if (argc > 2)
-				goto my_usage;
-			puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
-			set_altbank();
-			read_from_px_regs_altbank(1);
-			puts("Resetting board to boot from the other bank....\n");
-			set_px_go();
-		}
-
-	default:
-		goto my_usage;
-	}
-
-my_usage:
-	puts("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n");
-	puts("       reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n");
-	puts("       reset altbank [wd]\n");
-	puts("For example:   reset cf 40 2.5 10\n");
-	puts("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
-}
-
-
 /*
  * get_board_sys_clk
  *      Reads the FPGA on board for CONFIG_SYS_CLK_FREQ