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| author | Kumar Gala <galak@kernel.crashing.org> | 2007-11-29 02:18:59 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2007-12-11 22:34:20 -0600 |
| commit | a853d56c59b33415304531443633808736acfc6e (patch) | |
| tree | e0bc202284a139374ca085ca84383bee4d967614 /board/mpc8568mds | |
| parent | 04db400892da37b76a585e332a0c137954ad2015 (diff) | |
| download | u-boot-imx-a853d56c59b33415304531443633808736acfc6e.zip u-boot-imx-a853d56c59b33415304531443633808736acfc6e.tar.gz u-boot-imx-a853d56c59b33415304531443633808736acfc6e.tar.bz2 | |
Use standard LAWAR_TRGT_IF_* defines for LAW setup on 85xx
We already had defines for LAWAR_TRGT_IF_* that we should use
rather than creating new ones. Also, added some missing defines for
PCIE targets.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/mpc8568mds')
| -rw-r--r-- | board/mpc8568mds/init.S | 21 |
1 files changed, 7 insertions, 14 deletions
diff --git a/board/mpc8568mds/init.S b/board/mpc8568mds/init.S index 38ba9c7..e36036d 100644 --- a/board/mpc8568mds/init.S +++ b/board/mpc8568mds/init.S @@ -28,12 +28,6 @@ #include <config.h> #include <mpc85xx.h> -#define LAWAR_TRGT_PCI1 0x00000000 -#define LAWAR_TRGT_PCIE1 0x00200000 -#define LAWAR_TRGT_RIO 0x00c00000 -#define LAWAR_TRGT_LBC 0x00400000 -#define LAWAR_TRGT_DDR 0x00f00000 - /* * TLB0 and TLB1 Entries * @@ -216,27 +210,26 @@ tlb1_entry: */ #define LAWBAR0 0 -#define LAWAR0 ((LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) +#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) #define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) #define LAWBAR2 ((CFG_PCIE1_MEM_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) #define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M)) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M)) #define LAWBAR4 ((CFG_PCIE1_IO_PHYS>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_8M)) - +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_8M)) #define LAWBAR5 ((CFG_SRIO_MEM_BASE>>12) & 0xfffff) -#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) +#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) /* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */ #define LAWBAR6 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) +#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) .section .bootpg, "ax" .globl law_entry |