summaryrefslogtreecommitdiff
path: root/board/mpc8560ads
diff options
context:
space:
mode:
authorSergei Shtylyov <sshtylyov@ru.mvista.com>2006-12-27 22:07:15 +0300
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2007-04-23 19:58:28 -0500
commit362dd83077ac04c0296bca3e824ec2fb3d44d9d6 (patch)
treee344e1c88620ee50acc4262a00f104e3b478c9c2 /board/mpc8560ads
parent96629cbabdb727d4a5e62542deefc01d498db6dc (diff)
downloadu-boot-imx-362dd83077ac04c0296bca3e824ec2fb3d44d9d6.zip
u-boot-imx-362dd83077ac04c0296bca3e824ec2fb3d44d9d6.tar.gz
u-boot-imx-362dd83077ac04c0296bca3e824ec2fb3d44d9d6.tar.bz2
Fix PCI I/O space mapping on Freescale MPC85x0ADS
The PCI I/O space mapping for Freescale MPC8540ADS board was broken by commit 52c7a68b8d587ebcf5a6b051b58b3d3ffa377ddc which failed to update the #define's describing the local address window used for the PCI I/O space accesses -- fix this and carry over the necessary changes into the MPC8560ADS code since the PCI I/O space mapping was also broken for this board (by the earlier commit 087454609e47295443af793a282cddcd91a5f49c). Add the comments clarifying how the PCI I/O space must be mapped to all the MPC85xx board config. headers. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> board/mpc8540ads/init.S | 4 ++-- board/mpc8560ads/init.S | 4 ++-- include/configs/MPC8540ADS.h | 5 ++--- include/configs/MPC8541CDS.h | 2 +- include/configs/MPC8548CDS.h | 2 +- include/configs/MPC8560ADS.h | 8 ++++---- 6 files changed, 12 insertions(+), 13 deletions(-)
Diffstat (limited to 'board/mpc8560ads')
-rw-r--r--board/mpc8560ads/init.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/board/mpc8560ads/init.S b/board/mpc8560ads/init.S
index 242cb9f..544fde9 100644
--- a/board/mpc8560ads/init.S
+++ b/board/mpc8560ads/init.S
@@ -260,8 +260,8 @@ tlb1_entry:
#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
-#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
-#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
+#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
+#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_1M))
/*
* Rapid IO at 0xc000_0000 for 512 M