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| author | Timur Tabi <timur@freescale.com> | 2007-04-30 13:59:50 -0500 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2007-05-01 12:10:26 -0500 |
| commit | f64702b7fc8f8df39d31add770df6e372f9e9ce3 (patch) | |
| tree | d5a47b8ce01f17475dd7cde4cd32abc19774aeca /board/mpc8349itx/mpc8349itx.c | |
| parent | 54b2d434ae9d01787936f34fe1759cf3d7624ae3 (diff) | |
| download | u-boot-imx-f64702b7fc8f8df39d31add770df6e372f9e9ce3.zip u-boot-imx-f64702b7fc8f8df39d31add770df6e372f9e9ce3.tar.gz u-boot-imx-f64702b7fc8f8df39d31add770df6e372f9e9ce3.tar.bz2 | |
Fix memory initialization on MPC8349E-mITX
Define CFG_DDR_SDRAM_CLK_CNTL for the MPC8349E-mITX and MPC8349E-mITX-GP.
This allows ddr->sdram_clk_cntl to be properly initialized. This is necessary
on some ITX boards, notably those with a revision 3.1 CPU.
Also change spd_sdram() in cpu/mpc83xx/spd_sdram.c to not write anything into
ddr->sdram_clk_cntl if CFG_DDR_SDRAM_CLK_CNTL is not defined.
Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-by: Michael Benedict <MBenedict@twacs.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'board/mpc8349itx/mpc8349itx.c')
| -rw-r--r-- | board/mpc8349itx/mpc8349itx.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/board/mpc8349itx/mpc8349itx.c b/board/mpc8349itx/mpc8349itx.c index 2b3ded1..178b1d3 100644 --- a/board/mpc8349itx/mpc8349itx.c +++ b/board/mpc8349itx/mpc8349itx.c @@ -80,8 +80,7 @@ int fixed_sdram(void) im->ddr.sdram_interval = (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT); - im->ddr.sdram_clk_cntl = - DDR_SDRAM_CLK_CNTL_SS_EN | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05; + im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; udelay(200); |