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authorwdenk <wdenk>2003-09-18 10:45:21 +0000
committerwdenk <wdenk>2003-09-18 10:45:21 +0000
commit65bd0e284bbe08fdd6d2787d0698fe274d6aab13 (patch)
tree356a8f792fe0796080b00c28c0367aa803ec5c41 /board/mpc8266ads
parent206c60cbea71c89ac1c33ae49aa7cfa3bf6938cd (diff)
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* Patch by Rune Torgersen, 17 Sep 2003:
- Fixes for MPC8266 default config - Allow eth_loopback_test() on 8260 to use a subset of the FCC's
Diffstat (limited to 'board/mpc8266ads')
-rw-r--r--board/mpc8266ads/mpc8266ads.c14
1 files changed, 12 insertions, 2 deletions
diff --git a/board/mpc8266ads/mpc8266ads.c b/board/mpc8266ads/mpc8266ads.c
index fd11162..68a59a6 100644
--- a/board/mpc8266ads/mpc8266ads.c
+++ b/board/mpc8266ads/mpc8266ads.c
@@ -427,7 +427,7 @@ long int initdram(int board_type)
bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
sda10 = sdam + 2;
#else
- sdam = cols - 6;
+ sdam = cols + banks - 8;
bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
sda10 = sdam;
#endif
@@ -557,9 +557,18 @@ long int initdram(int board_type)
printf("SDRAM configuration read from SPD\n");
printf("\tSize per side = %dMB\n", sdram_size >> 20);
printf("\tOrganization: %d sides, %d banks, %d Columns, %d Rows, Data width = %d bits\n", chipselects, 1<<(banks), cols, rows, data_width);
- printf("\tRefresh rate = %d, CAS latency = %d\n", psrt, caslatency);
+ printf("\tRefresh rate = %d, CAS latency = %d", psrt, caslatency);
+#if(CONFIG_PBI == 0) /* bank-based interleaving */
+ printf(", Using Bank Based Interleave\n");
+#else
+ printf(", Using Page Based Interleave\n");
+#endif
printf("\tTotal size: ");
+ /* this delay only needed for original 16MB DIMM...
+ * Not needed for any other memory configuration */
+ if ((sdram_size * chipselects) == (16 *1024 *1024))
+ udelay (250000);
return (sdram_size * chipselects);
/*return (16 * 1024 * 1024);*/
}
@@ -575,3 +584,4 @@ void pci_init_board(void)
pci_mpc8250_init(&hose);
}
#endif
+