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authorroy zang <tie-fei.zang@freescale.com>2006-12-04 17:54:21 +0800
committerZang Tiefei <roy@bus.ap.freescale.net>2006-12-04 17:54:21 +0800
commit4dbcd69e3e2776ea334590d5768e3692c5fae5c1 (patch)
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Introduce PLL_CFG[0:4] table for processor 7448/7447A/7455/7457. The original
multiplier table can not refect the real PLL clock behavior of these processors. Please refer to the hardware specification for detailed information of the corresponding processors. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
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