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| author | Thierry Reding <treding@nvidia.com> | 2014-12-09 22:25:23 -0700 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2014-12-18 13:21:41 -0700 |
| commit | d1e5b4065ee14a6dbabd9318a8f73194c6536d6e (patch) | |
| tree | 1384c72c6af679be2a35dc0d60797f23468c7351 /board/micronas/vct/dcgu.h | |
| parent | 1dfdd9ba4e699562a3b282f4fb5efe4c80e6e8c7 (diff) | |
| download | u-boot-imx-d1e5b4065ee14a6dbabd9318a8f73194c6536d6e.zip u-boot-imx-d1e5b4065ee14a6dbabd9318a8f73194c6536d6e.tar.gz u-boot-imx-d1e5b4065ee14a6dbabd9318a8f73194c6536d6e.tar.bz2 | |
ARM: tegra: Enable non-cached memory
Some boards, most notably those with a PCIe ethernet NIC, require this
to avoid cache coherency problems. Since the option adds very little
code and overhead enable it across all Tegra generations. Other drivers
may also start supporting this functionality at some point, so enabling
it now will automatically reap the benefits later on.
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'board/micronas/vct/dcgu.h')
0 files changed, 0 insertions, 0 deletions