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| author | Wolfgang Denk <wd@nyx.denx.de> | 2006-03-06 13:03:37 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@nyx.denx.de> | 2006-03-06 13:03:37 +0100 |
| commit | bfc81252c0de3bfcf92c7c35bc04341fb33e4e4e (patch) | |
| tree | d2b832bf54040b49a8518b63620f2774398fa8d5 /board/mcc200/mt48lc8m32b2-6-7.h | |
| parent | 4e3ccd26925e5ada78dd89779838f052dffe3e67 (diff) | |
| download | u-boot-imx-bfc81252c0de3bfcf92c7c35bc04341fb33e4e4e.zip u-boot-imx-bfc81252c0de3bfcf92c7c35bc04341fb33e4e4e.tar.gz u-boot-imx-bfc81252c0de3bfcf92c7c35bc04341fb33e4e4e.tar.bz2 | |
Minor code cleanup
Diffstat (limited to 'board/mcc200/mt48lc8m32b2-6-7.h')
| -rw-r--r-- | board/mcc200/mt48lc8m32b2-6-7.h | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/board/mcc200/mt48lc8m32b2-6-7.h b/board/mcc200/mt48lc8m32b2-6-7.h index 6c2b2b3..73dcd5c 100644 --- a/board/mcc200/mt48lc8m32b2-6-7.h +++ b/board/mcc200/mt48lc8m32b2-6-7.h @@ -4,27 +4,9 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ -//#define SDRAM_MODE 0x00cc0000 // CL-3 BURST-8 -> Mode Register—MBAR + 0x0100 -//#define SDRAM_CONTROL 0x501f0000 // Control Register—MBAR + 0x0104 -//#define SDRAM_CONFIG1 0xe2329000 // Delays between commands -> Configuration Register 1—MBAR + 0x0108 -//#define SDRAM_CONFIG2 0x46e70000 // Delays between commands -> Configuration Register 2—MBAR + 0x010C -//Christian -//#define SDRAM_MODE 0x00cd0000 // CL-3 BURST-8 -> Mode Register—MBAR + 0x0100 -//#define SDRAM_CONTROL 0x501f0000 // Control Register—MBAR + 0x0104 -//#define SDRAM_CONFIG1 0xd2322900 // Delays between commands -> Configuration Register 1—MBAR + 0x0108 -//#define SDRAM_CONFIG2 0x8ad70000 // Delays between commands -> Configuration Register 2—MBAR + 0x010C - -//###CHD: ordentliche Doku dazu! CAS=2, etc. -//STefan #define SDRAM_MODE 0x008d0000 // CL-3 BURST-8 -> Mode Register—MBAR + 0x0100 #define SDRAM_CONTROL 0x504f0000 // Control Register—MBAR + 0x0104 #define SDRAM_CONFIG1 0xc2222900 // Delays between commands -> Configuration Register 1—MBAR + 0x0108 #define SDRAM_CONFIG2 0x88c70000 // Delays between commands -> Configuration Register 2—MBAR + 0x010C - - -#else -#error CONFIG_MPC5200 not defined, please set parameters for your sdram controller in mt48lc8m32b2.h -#endif |