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| author | Kumar Gala <galak@kernel.crashing.org> | 2006-03-20 10:42:05 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2006-03-20 10:42:05 -0600 |
| commit | f8edca2e9a128f526b1fe6f997f7adb852cf5b3c (patch) | |
| tree | 92deb9ddf1153c64ff1ced9392816e60b4ecaa03 /board/mcc200/mt48lc8m32b2-6-7.h | |
| parent | 79582020313e6d992a3bac71cf3a9b337f9ac7f7 (diff) | |
| parent | 7b4fd36b0322ec98836a8459d9be80e2777fdc05 (diff) | |
| download | u-boot-imx-f8edca2e9a128f526b1fe6f997f7adb852cf5b3c.zip u-boot-imx-f8edca2e9a128f526b1fe6f997f7adb852cf5b3c.tar.gz u-boot-imx-f8edca2e9a128f526b1fe6f997f7adb852cf5b3c.tar.bz2 | |
Merge branch 'origin'
Conflicts:
CHANGELOG
Diffstat (limited to 'board/mcc200/mt48lc8m32b2-6-7.h')
| -rw-r--r-- | board/mcc200/mt48lc8m32b2-6-7.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/board/mcc200/mt48lc8m32b2-6-7.h b/board/mcc200/mt48lc8m32b2-6-7.h new file mode 100644 index 0000000..13aebbd --- /dev/null +++ b/board/mcc200/mt48lc8m32b2-6-7.h @@ -0,0 +1,12 @@ +/* + * Configuration Registers for the MT48LC8M32B2 SDRAM on the MPC5200 platform + */ + +#define SDRAM_DDR 0 /* is SDR */ + +/* Settings for XLB = 132 MHz */ + +#define SDRAM_MODE 0x008d0000 /* CL-3 BURST-8 -> Mode Register MBAR + 0x0100 */ +#define SDRAM_CONTROL 0x504f0000 /* Control Register MBAR + 0x0104 */ +#define SDRAM_CONFIG1 0xc2222900 /* Delays between commands -> Configuration Register 1 MBAR + 0x0108 */ +#define SDRAM_CONFIG2 0x88c70000 /* Delays between commands -> Configuration Register 2 MBAR + 0x010C */ |