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authorroy zang <tie-fei.zang@freescale.com>2006-11-29 09:45:03 +0800
committerZang Tiefei <roy@bus.ap.freescale.net>2006-11-29 09:45:03 +0800
commit6bd87c0aeea441c49d59fd542b84a9be88d08b17 (patch)
treee450a5f1e69a78a203a1e15167d7fefa43c5ce7e /board/mcc200/mcc200.c
parent0a8eb59983047ae3bcc0babf3ee4d10d01abe7da (diff)
parentd2c83f549378fb3fc34cb3c2e62fd772fbf8b68b (diff)
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Solve the copyright conflicts when merging 'master' into hpc2.
Merge branch 'master' into hpc2 Conflicts: drivers/cfi_flash.c
Diffstat (limited to 'board/mcc200/mcc200.c')
-rw-r--r--board/mcc200/mcc200.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c
index 71a691b..5d74bde 100644
--- a/board/mcc200/mcc200.c
+++ b/board/mcc200/mcc200.c
@@ -27,6 +27,7 @@
#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
+#include <asm/processor.h>
/* Two MT48LC8M32B2 for 32 MB */
/* #include "mt48lc8m32b2-6-7.h" */
@@ -98,6 +99,7 @@ long int initdram (int board_type)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
+ uint svr, pvr;
#ifndef CFG_RAMBOOT
ulong test1, test2;
@@ -192,6 +194,22 @@ long int initdram (int board_type)
#endif /* CFG_RAMBOOT */
+ /*
+ * On MPC5200B we need to set the special configuration delay in the
+ * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+ * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+ *
+ * "The SDelay should be written to a value of 0x00000004. It is
+ * required to account for changes caused by normal wafer processing
+ * parameters."
+ */
+ svr = get_svr();
+ pvr = get_pvr();
+ if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+ *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+ __asm__ volatile ("sync");
+ }
+
return dramsize + dramsize2;
}