diff options
| author | Fabio Estevam <festevam@gmail.com> | 2011-08-19 03:28:10 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-09-04 11:36:11 +0200 |
| commit | 9691c5b96d889b1d4c8908c449b47d80699dc915 (patch) | |
| tree | 9e1476e7354da652274b1f7b95fbed7c59ce766c /board/mbx8xx/csr.h | |
| parent | 9db1bfa110ac411ab3468e817f7f74b2439eb8c8 (diff) | |
| download | u-boot-imx-9691c5b96d889b1d4c8908c449b47d80699dc915.zip u-boot-imx-9691c5b96d889b1d4c8908c449b47d80699dc915.tar.gz u-boot-imx-9691c5b96d889b1d4c8908c449b47d80699dc915.tar.bz2 | |
mx53: ddr3: Update DD3 initialization
Updated mx53 ddr3 script in order to align with the latest Freescale version from July 8, 2011:
-change ESDREF[REF_SEL]=01 (for 32KHz), from incorrect setting of 00 (64KHz)
-change DDR3 MR0 write to "setmem /32 0x63fd901c = 0x052080b0" from
"0x092080b0". This changes write recovery from 8 clocks to 6 clocks
(in line with ESDCFG1[tWR])
Signed-off-by: Lily Zhang <r58066@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'board/mbx8xx/csr.h')
0 files changed, 0 insertions, 0 deletions