rename CFG_ macros to CONFIG_SYS

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

4 files changed, 42 insertions, 42 deletions

diff --git a/board/matrix_vision/mvbc_p/mvbc_p.c b/board/matrix_vision/mvbc_p/mvbc_p.c
index c88c4a6..a300342 100644
--- a/board/matrix_vision/mvbc_p/mvbc_p.c
+++ b/board/matrix_vision/mvbc_p/mvbc_p.c
@@ -85,9 +85,9 @@ phys_addr_t initdram (int board_type)
 
 	/* find RAM size using SDRAM CS0 only */
 	sdram_start(0);
-	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	sdram_start(1);
-	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	if (test1 > test2) {
 		sdram_start(0);
 		dramsize = test1;
@@ -193,13 +193,13 @@ void flash_preinit(void)
 
 void flash_afterinit(ulong size)
 {
-	out_be32((u32*)MPC5XXX_BOOTCS_START, START_REG(CFG_BOOTCS_START |
+	out_be32((u32*)MPC5XXX_BOOTCS_START, START_REG(CONFIG_SYS_BOOTCS_START |
 		size));
-	out_be32((u32*)MPC5XXX_CS0_START, START_REG(CFG_BOOTCS_START |
+	out_be32((u32*)MPC5XXX_CS0_START, START_REG(CONFIG_SYS_BOOTCS_START |
 		size));
-	out_be32((u32*)MPC5XXX_BOOTCS_STOP, STOP_REG(CFG_BOOTCS_START | size,
+	out_be32((u32*)MPC5XXX_BOOTCS_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size,
 		size));
-	out_be32((u32*)MPC5XXX_CS0_STOP, STOP_REG(CFG_BOOTCS_START | size,
+	out_be32((u32*)MPC5XXX_CS0_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size,
 		size));
 }
 
diff --git a/board/matrix_vision/mvblm7/fpga.c b/board/matrix_vision/mvblm7/fpga.c
index a60af01..7527d16 100644
--- a/board/matrix_vision/mvblm7/fpga.c
+++ b/board/matrix_vision/mvblm7/fpga.c
@@ -79,7 +79,7 @@ int fpga_null_fn(int cookie)
 
 int fpga_config_fn(int assert, int flush, int cookie)
 {
-	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
 	u32 dvo = gpio->dat;
 
@@ -97,7 +97,7 @@ int fpga_config_fn(int assert, int flush, int cookie)
 
 int fpga_done_fn(int cookie)
 {
-	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
 	int result = 0;
 
@@ -114,7 +114,7 @@ int fpga_done_fn(int cookie)
 
 int fpga_status_fn(int cookie)
 {
-	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
 	int result = 0;
 
@@ -130,7 +130,7 @@ int fpga_status_fn(int cookie)
 
 int fpga_clk_fn(int assert_clk, int flush, int cookie)
 {
-	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
 	u32 dvo = gpio->dat;
 
@@ -148,7 +148,7 @@ int fpga_clk_fn(int assert_clk, int flush, int cookie)
 
 static inline int _write_fpga(u8 val, int dump)
 {
-	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
 	int i;
 	u32 dvo = gpio->dat;
diff --git a/board/matrix_vision/mvblm7/mvblm7.c b/board/matrix_vision/mvblm7/mvblm7.c
index 3dcff67..6984af9 100644
--- a/board/matrix_vision/mvblm7/mvblm7.c
+++ b/board/matrix_vision/mvblm7/mvblm7.c
@@ -38,50 +38,50 @@
 
 int fixed_sdram(void)
 {
-	volatile immap_t *im = (immap_t *)CFG_IMMR;
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize = 0;
 	u32 ddr_size;
 	u32 ddr_size_log2;
 
-	msize = CFG_DDR_SIZE;
+	msize = CONFIG_SYS_DDR_SIZE;
 	for (ddr_size = msize << 20, ddr_size_log2 = 0;
 	     (ddr_size > 1);
 	     ddr_size = ddr_size >> 1, ddr_size_log2++) {
 		if (ddr_size & 1)
 			return -1;
 	}
-	im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
 	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) &
 		LAWAR_SIZE);
 
-	im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
-	im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
-	im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
-	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
-	im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
-	im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
-	im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CFG_DDR_MODE;
-	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
-	im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
+	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
 
 	udelay(300);
 
 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 
-	return CFG_DDR_SIZE;
+	return CONFIG_SYS_DDR_SIZE;
 }
 
 phys_size_t initdram(int board_type)
 {
-	volatile immap_t *im = (immap_t *) CFG_IMMR;
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
 		return -1;
 
-	im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
 	msize = fixed_sdram();
 
 	/* return total bus RAM size(bytes) */
@@ -132,14 +132,14 @@ int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 
 void spi_cs_activate(struct spi_slave *slave)
 {
-	volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
+	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
 
 	iopd->dat &= ~MVBLM7_MMC_CS;
 }
 
 void spi_cs_deactivate(struct spi_slave *slave)
 {
-	volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
+	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
 
 	iopd->dat |= ~MVBLM7_MMC_CS;
 }
diff --git a/board/matrix_vision/mvblm7/pci.c b/board/matrix_vision/mvblm7/pci.c
index ef34a6b..9f31719 100644
--- a/board/matrix_vision/mvblm7/pci.c
+++ b/board/matrix_vision/mvblm7/pci.c
@@ -52,21 +52,21 @@ int mvblm7_load_fpga(void)
 
 static struct pci_region pci_regions[] = {
 	{
-		bus_start: CFG_PCI1_MEM_BASE,
-		phys_start: CFG_PCI1_MEM_PHYS,
-		size: CFG_PCI1_MEM_SIZE,
+		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+		size: CONFIG_SYS_PCI1_MEM_SIZE,
 		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
 	},
 	{
-		bus_start: CFG_PCI1_MMIO_BASE,
-		phys_start: CFG_PCI1_MMIO_PHYS,
-		size: CFG_PCI1_MMIO_SIZE,
+		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+		size: CONFIG_SYS_PCI1_MMIO_SIZE,
 		flags: PCI_REGION_MEM
 	},
 	{
-		bus_start: CFG_PCI1_IO_BASE,
-		phys_start: CFG_PCI1_IO_PHYS,
-		size: CFG_PCI1_IO_SIZE,
+		bus_start: CONFIG_SYS_PCI1_IO_BASE,
+		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+		size: CONFIG_SYS_PCI1_IO_SIZE,
 		flags: PCI_REGION_IO
 	}
 };
@@ -85,7 +85,7 @@ void pci_init_board(void)
 	struct pci_region *reg[] = { pci_regions };
 
 	load_fpga = 1;
-	immr = (immap_t *) CFG_IMMR;
+	immr = (immap_t *) CONFIG_SYS_IMMR;
 	clk = (clk83xx_t *) &immr->clk;
 	pci_ctrl = immr->pci_ctrl;
 	pci_law = immr->sysconf.pcilaw;
@@ -121,10 +121,10 @@ void pci_init_board(void)
 	for (i = 0; i < 1000; ++i)
 		udelay(1000);
 
-	pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
 	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_1GB;
 
-	pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
 	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
 
 	warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;