Merge branch 'master' of git://git.denx.de/u-boot-arm

Conflicts:
	cpu/arm1176/cpu.c
	cpu/arm1176/start.S
	cpu/arm_cortexa8/s5pc1xx/Makefile
	cpu/arm_cortexa8/s5pc1xx/clock.c
	drivers/serial/serial_s5p.c
	include/asm-arm/arch-s5pc1xx/clk.h
	include/asm-arm/arch-s5pc1xx/gpio.h
	include/asm-arm/arch-s5pc1xx/uart.h

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

8 files changed, 730 insertions, 0 deletions

diff --git a/board/matrix_vision/mvsmr/Makefile b/board/matrix_vision/mvsmr/Makefile
new file mode 100644
index 0000000..b179e6d
--- /dev/null
+++ b/board/matrix_vision/mvsmr/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004-2008
+# Matrix-Vision GmbH, info@matrix-vision.de
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o fpga.o
+
+SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+	        $(AR) $(ARFLAGS) $@ $(OBJS)
+	@mkimage -T script -C none -n mvSMR_Script -d bootscript bootscript.img
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/board/matrix_vision/mvsmr/bootscript b/board/matrix_vision/mvsmr/bootscript
new file mode 100644
index 0000000..02c802c
--- /dev/null
+++ b/board/matrix_vision/mvsmr/bootscript
@@ -0,0 +1,42 @@
+echo
+echo "==== running autoscript ===="
+echo
+setenv boot24 'bootm ${kernel_boot} ${mv_initrd_addr_ram}'
+setenv ramkernel 'setenv kernel_boot ${loadaddr}'
+setenv flashkernel 'setenv kernel_boot ${mv_kernel_addr}'
+setenv cpird 'cp ${mv_initrd_addr} ${mv_initrd_addr_ram} ${mv_initrd_length}'
+setenv bootfromflash run flashkernel cpird addcons boot24
+setenv bootfromnet 'tftp ${mv_initrd_addr_ram} ${initrd_name};run ramkernel'
+if test ${console} = yes;
+then
+setenv addcons 'setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8'
+else
+setenv addcons 'setenv bootargs ${bootargs} console=tty0'
+fi
+setenv set_static_ip 'setenv ipaddr ${static_ipaddr}'
+setenv set_static_nm 'setenv netmask ${static_netmask}'
+setenv set_static_gw 'setenv gatewayip ${static_gateway}'
+setenv set_ip 'setenv ip ${ipaddr}::${gatewayip}:${netmask}'
+if test ${servicemode} != yes;
+then
+  echo "=== forced flash mode ==="
+  run set_static_ip set_static_nm set_static_gw set_ip bootfromflash
+fi
+if test ${autoscript_boot} != no;
+then
+  if test ${netboot} = yes;
+  then
+    bootp
+    if test $? = 0;
+    then
+      echo "=== bootp succeeded -> netboot ==="
+      run set_ip bootfromnet addcons boot24
+    else
+      echo "=== netboot failed ==="
+    fi
+  fi
+  echo "=== bootfromflash ==="
+  run set_static_ip set_static_nm set_static_gw set_ip bootfromflash
+else
+  echo "=== boot stopped with autoscript_boot no ==="
+fi
diff --git a/board/matrix_vision/mvsmr/config.mk b/board/matrix_vision/mvsmr/config.mk
new file mode 100644
index 0000000..b1da812
--- /dev/null
+++ b/board/matrix_vision/mvsmr/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+TEXT_BASE = 0xFF800000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
+LDSCRIPT := $(SRCTREE)/board/matrix_vision/mvsmr/u-boot.lds
diff --git a/board/matrix_vision/mvsmr/fpga.c b/board/matrix_vision/mvsmr/fpga.c
new file mode 100644
index 0000000..6320a69
--- /dev/null
+++ b/board/matrix_vision/mvsmr/fpga.c
@@ -0,0 +1,129 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * (C) Copyright 2010
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <spartan3.h>
+#include <command.h>
+#include <asm/io.h>
+#include "fpga.h"
+#include "mvsmr.h"
+
+Xilinx_Spartan3_Slave_Serial_fns fpga_fns = {
+	fpga_pre_config_fn,
+	fpga_pgm_fn,
+	fpga_clk_fn,
+	fpga_init_fn,
+	fpga_done_fn,
+	fpga_wr_fn,
+	0
+};
+
+Xilinx_desc spartan3 = {
+	Xilinx_Spartan2,
+	slave_serial,
+	XILINX_XC3S200_SIZE,
+	(void *) &fpga_fns,
+	0,
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mvsmr_init_fpga(void)
+{
+	fpga_init();
+	fpga_add(fpga_xilinx, &spartan3);
+
+	return 1;
+}
+
+int fpga_init_fn(int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+	if (in_be32(&gpio->simple_ival) & FPGA_CONFIG)
+		return 0;
+
+	return 1;
+}
+
+int fpga_done_fn(int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+	int result = 0;
+
+	udelay(10);
+	if (in_be32(&gpio->simple_ival) & FPGA_DONE)
+		result = 1;
+
+	return result;
+}
+
+int fpga_pgm_fn(int assert, int flush, int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+	if (!assert)
+		setbits_8(&gpio->sint_dvo, FPGA_STATUS);
+	else
+		clrbits_8(&gpio->sint_dvo, FPGA_STATUS);
+
+	return assert;
+}
+
+int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+	if (assert_clk)
+		setbits_be32(&gpio->simple_dvo, FPGA_CCLK);
+	else
+		clrbits_be32(&gpio->simple_dvo, FPGA_CCLK);
+
+	return assert_clk;
+}
+
+int fpga_wr_fn(int assert_write, int flush, int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+	if (assert_write)
+		setbits_be32(&gpio->simple_dvo, FPGA_DIN);
+	else
+		clrbits_be32(&gpio->simple_dvo, FPGA_DIN);
+
+	return assert_write;
+}
+
+int fpga_pre_config_fn(int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+	setbits_8(&gpio->sint_dvo, FPGA_STATUS);
+
+	return 0;
+}
diff --git a/board/matrix_vision/mvsmr/fpga.h b/board/matrix_vision/mvsmr/fpga.h
new file mode 100644
index 0000000..ee690e6
--- /dev/null
+++ b/board/matrix_vision/mvsmr/fpga.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2008
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+extern int mvsmr_init_fpga(void);
+
+extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
+extern int fpga_init_fn(int cookie);
+extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
+extern int fpga_wr_fn(int assert_write, int flush, int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_pre_config_fn(int cookie);
diff --git a/board/matrix_vision/mvsmr/mvsmr.c b/board/matrix_vision/mvsmr/mvsmr.c
new file mode 100644
index 0000000..69655c4
--- /dev/null
+++ b/board/matrix_vision/mvsmr/mvsmr.c
@@ -0,0 +1,264 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2005-2010
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <malloc.h>
+#include <pci.h>
+#include <i2c.h>
+#include <fpga.h>
+#include <environment.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include "fpga.h"
+#include "mvsmr.h"
+#include "../common/mv_common.h"
+
+#define SDRAM_DDR	1
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x715f0f00
+#define SDRAM_CONFIG1	0xd3722930
+#define SDRAM_CONFIG2	0x46770000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void sdram_start(int hi_addr)
+{
+	long hi_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 |
+		hi_bit);
+
+	/* precharge all banks */
+	out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 |
+		hi_bit);
+
+	/* set mode register: extended mode */
+	out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
+
+	/* set mode register: reset DLL */
+	out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
+
+	/* precharge all banks */
+	out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 |
+		hi_bit);
+
+	/* auto refresh */
+	out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 |
+		hi_bit);
+
+	/* set mode register */
+	out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
+
+	/* normal operation */
+	out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit);
+}
+
+phys_addr_t initdram(int board_type)
+{
+	ulong dramsize = 0;
+	ulong test1,
+	      test2;
+
+	/* setup SDRAM chip selects */
+	out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);
+
+	/* setup config registers */
+	out_be32((u32 *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
+	out_be32((u32 *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else
+		dramsize = test2;
+
+	if (dramsize < (1 << 20))
+		dramsize = 0;
+
+	if (dramsize > 0)
+		out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x13 +
+			__builtin_ffs(dramsize >> 20) - 1);
+	else
+		out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0);
+
+	return dramsize;
+}
+
+void mvsmr_init_gpio(void)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+	struct mpc5xxx_wu_gpio *wu_gpio =
+		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+	struct mpc5xxx_gpt_0_7 *timers = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+
+	printf("Ports : 0x%08x\n", gpio->port_config);
+	printf("PORCFG: 0x%08x\n", in_be32((unsigned *)MPC5XXX_CDM_PORCFG));
+
+	out_be32(&gpio->simple_ddr, SIMPLE_DDR);
+	out_be32(&gpio->simple_dvo, SIMPLE_DVO);
+	out_be32(&gpio->simple_ode, SIMPLE_ODE);
+	out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN);
+
+	out_8(&gpio->sint_ode, SINT_ODE);
+	out_8(&gpio->sint_ddr, SINT_DDR);
+	out_8(&gpio->sint_dvo, SINT_DVO);
+	out_8(&gpio->sint_inten, SINT_INTEN);
+	out_be16(&gpio->sint_itype, SINT_ITYPE);
+	out_8(&gpio->sint_gpioe, SINT_GPIOEN);
+
+	out_8(&wu_gpio->ode, WKUP_ODE);
+	out_8(&wu_gpio->ddr, WKUP_DIR);
+	out_8(&wu_gpio->dvo, WKUP_DO);
+	out_8(&wu_gpio->enable, WKUP_EN);
+
+	out_be32(&timers->gpt0.emsr, 0x00000234); /* OD output high */
+	out_be32(&timers->gpt1.emsr, 0x00000234);
+	out_be32(&timers->gpt2.emsr, 0x00000234);
+	out_be32(&timers->gpt3.emsr, 0x00000234);
+	out_be32(&timers->gpt4.emsr, 0x00000234);
+	out_be32(&timers->gpt5.emsr, 0x00000234);
+	out_be32(&timers->gpt6.emsr, 0x00000024); /* push-pull output low */
+	out_be32(&timers->gpt7.emsr, 0x00000024);
+}
+
+int misc_init_r(void)
+{
+	char *s = getenv("reset_env");
+
+	if (s) {
+		printf(" === FACTORY RESET ===\n");
+		mv_reset_environment();
+		saveenv();
+	}
+
+	return -1;
+}
+
+void mvsmr_get_dbg_present(void)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)MPC5XXX_PSC1;
+
+	if (in_be32(&gpio->simple_ival) & COP_PRESENT) {
+		setenv("dbg_present", "no\0");
+		setenv("bootstopkey", "abcdefghijklmnopqrstuvwxyz\0");
+	} else {
+		setenv("dbg_present", "yes\0");
+		setenv("bootstopkey", "s\0");
+		setbits_8(&psc->command, PSC_RX_ENABLE);
+	}
+}
+
+void mvsmr_get_service_mode(void)
+{
+	struct mpc5xxx_wu_gpio *wu_gpio =
+		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+
+	if (in_8(&wu_gpio->ival) & SERVICE_MODE)
+		setenv("servicemode", "no\0");
+	else
+		setenv("servicemode", "yes\0");
+}
+
+int mvsmr_get_mac(void)
+{
+	unsigned char mac[6];
+	struct mpc5xxx_wu_gpio *wu_gpio =
+		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+
+	if (in_8(&wu_gpio->ival) & LAN_PRSNT) {
+		setenv("lan_present", "no\0");
+		return -1;
+	} else
+		setenv("lan_present", "yes\0");
+
+	i2c_read(0x50, 0, 1, mac, 6);
+
+	eth_setenv_enetaddr("ethaddr", mac);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	mvsmr_init_gpio();
+	printf("Board: Matrix Vision mvSMR\n");
+
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	clrbits_be32((u32 *)MPC5XXX_BOOTCS_CFG, 0x1);
+}
+
+void flash_afterinit(ulong size)
+{
+	out_be32((u32 *)MPC5XXX_BOOTCS_START,
+		START_REG(CONFIG_SYS_BOOTCS_START | size));
+	out_be32((u32 *)MPC5XXX_CS0_START,
+		START_REG(CONFIG_SYS_BOOTCS_START | size));
+	out_be32((u32 *)MPC5XXX_BOOTCS_STOP,
+		STOP_REG(CONFIG_SYS_BOOTCS_START | size, size));
+	out_be32((u32 *)MPC5XXX_CS0_STOP,
+		STOP_REG(CONFIG_SYS_BOOTCS_START | size, size));
+}
+
+struct pci_controller hose;
+
+void pci_init_board(void)
+{
+	mvsmr_get_dbg_present();
+	mvsmr_get_service_mode();
+	mvsmr_init_fpga();
+	mv_load_fpga();
+	pci_mpc5xxx_init(&hose);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	if (!mvsmr_get_mac())
+		return cpu_eth_init(bis);
+
+	return pci_eth_init(bis);
+}
diff --git a/board/matrix_vision/mvsmr/mvsmr.h b/board/matrix_vision/mvsmr/mvsmr.h
new file mode 100644
index 0000000..b8320f1
--- /dev/null
+++ b/board/matrix_vision/mvsmr/mvsmr.h
@@ -0,0 +1,43 @@
+#include <pci.h>
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+#define FPGA_DIN	MPC5XXX_GPIO_SIMPLE_PSC3_0
+#define FPGA_CCLK	MPC5XXX_GPIO_SIMPLE_PSC3_1
+#define FPGA_DONE	MPC5XXX_GPIO_SIMPLE_PSC3_2
+#define FPGA_CONFIG	MPC5XXX_GPIO_SIMPLE_PSC3_3
+#define FPGA_STATUS	MPC5XXX_GPIO_SINT_PSC3_4
+#define S_FPGA_DIN	MPC5XXX_GPIO_SINT_PSC3_5
+#define S_FPGA_CCLK	MPC5XXX_GPIO_SIMPLE_PSC3_6
+#define S_FPGA_DONE	MPC5XXX_GPIO_SIMPLE_PSC3_7
+#define S_FPGA_CONFIG	MPC5XXX_GPIO_SINT_PSC3_8
+#define S_FPGA_STATUS	MPC5XXX_GPIO_WKUP_PSC3_9
+
+#define MAN_RST		MPC5XXX_GPIO_WKUP_PSC6_0
+#define WD_TS		MPC5XXX_GPIO_WKUP_PSC6_1
+#define WD_WDI		MPC5XXX_GPIO_SIMPLE_PSC6_2
+#define COP_PRESENT	MPC5XXX_GPIO_SIMPLE_PSC6_3
+#define SERVICE_MODE	MPC5XXX_GPIO_WKUP_6
+#define FLASH_RBY	MPC5XXX_GPIO_WKUP_7
+#define UART_EN1	MPC5XXX_GPIO_WKUP_PSC1_4
+#define LAN_PRSNT	MPC5XXX_GPIO_WKUP_PSC2_4
+
+#define SIMPLE_DDR	(FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI |\
+			 S_FPGA_CCLK)
+#define SIMPLE_DVO	(FPGA_CONFIG)
+#define SIMPLE_ODE	(FPGA_CONFIG)
+#define SIMPLE_GPIOEN	(FPGA_DIN | FPGA_CCLK | FPGA_DONE | FPGA_CONFIG |\
+			 S_FPGA_CCLK | S_FPGA_DONE | WD_WDI | COP_PRESENT)
+
+#define SINT_ODE	0x1
+#define SINT_DDR	0x3
+#define SINT_DVO	0x1
+#define SINT_INTEN	0
+#define SINT_ITYPE	0
+#define SINT_GPIOEN	(FPGA_STATUS | S_FPGA_DIN | S_FPGA_CONFIG)
+
+#define WKUP_ODE	(MAN_RST | S_FPGA_STATUS)
+#define WKUP_DIR	(MAN_RST | WD_TS | S_FPGA_STATUS)
+#define WKUP_DO		(MAN_RST | WD_TS | S_FPGA_STATUS)
+#define WKUP_EN		(MAN_RST | WD_TS | S_FPGA_STATUS | SERVICE_MODE |\
+			 FLASH_RBY | UART_EN1 | LAN_PRSNT)
diff --git a/board/matrix_vision/mvsmr/u-boot.lds b/board/matrix_vision/mvsmr/u-boot.lds
new file mode 100644
index 0000000..cfbb6ef
--- /dev/null
+++ b/board/matrix_vision/mvsmr/u-boot.lds
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) Copyright 2010
+ * André Schwarz, Matrix Vision GmbH, as@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within  */
+    /* the first two sectors (=8KB) of our S29GL flash chip */
+    cpu/mpc5xxx/start.o          (.text)
+    cpu/mpc5xxx/traps.o          (.text)
+    lib_generic/crc32.o         (.text)
+    lib_ppc/cache.o             (.text)
+    lib_ppc/time.o              (.text)
+
+    /* This is only needed to force failure if size of above code will ever */
+    /* increase and grow into reserved space. */
+    . = ALIGN(0x2000);	/* location counter has to be 0x4000 now */
+    . += 0x4000;	/* ->0x8000, i.e. move to env_offset */
+
+    . = env_offset;	/* ld error as soon as above ALIGN misplaces lc */
+    common/env_embedded.o        (.ppcenv)
+
+    *(.text)
+    *(.got1)
+    . = ALIGN(16);
+    *(.eh_frame)
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}