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author | Michal Simek <monstr@monstr.eu> | 2007-09-11 00:29:27 +0200 |
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committer | Michal Simek <monstr@monstr.eu> | 2007-09-11 00:29:27 +0200 |
commit | 9c73f4b81172bc9f1b8f132450e69bcfb5b960ca (patch) | |
tree | b20402ff5f80a91423b9d444ba5b947d36cd06ff /board/m5282evb/m5282evb.c | |
parent | 78cff50edba6b1508eb15c2f53ce966ac891eb9e (diff) | |
parent | e251e00d0db4b36d1d2b7e38fec43a7296b529a2 (diff) | |
download | u-boot-imx-9c73f4b81172bc9f1b8f132450e69bcfb5b960ca.zip u-boot-imx-9c73f4b81172bc9f1b8f132450e69bcfb5b960ca.tar.gz u-boot-imx-9c73f4b81172bc9f1b8f132450e69bcfb5b960ca.tar.bz2 |
Merge git://www.denx.de/git/u-boot
Diffstat (limited to 'board/m5282evb/m5282evb.c')
-rw-r--r-- | board/m5282evb/m5282evb.c | 61 |
1 files changed, 59 insertions, 2 deletions
diff --git a/board/m5282evb/m5282evb.c b/board/m5282evb/m5282evb.c index a08af68..243d6a4 100644 --- a/board/m5282evb/m5282evb.c +++ b/board/m5282evb/m5282evb.c @@ -22,14 +22,71 @@ */ #include <common.h> +#include <asm/immap.h> + +DECLARE_GLOBAL_DATA_PTR; int checkboard (void) { - puts ("MOTOROLA M5272EVB Evaluation Board\n"); + puts ("Board: Freescale M5282EVB Evaluation Board\n"); return 0; } long int initdram (int board_type) { - return 0x1000000; + u32 dramsize, i, dramclk; + + dramsize = CFG_SDRAM_SIZE * 0x100000; + for (i = 0x13; i < 0x20; i++) { + if (dramsize == (1 << i)) + break; + } + i--; + + if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE)) + { + dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ); + + /* Initialize DRAM Control Register: DCR */ + MCFSDRAMC_DCR = (0 + | MCFSDRAMC_DCR_RTIM_6 + | MCFSDRAMC_DCR_RC((15 * dramclk)>>4)); + + /* Initialize DACR0 */ + MCFSDRAMC_DACR0 = (0 + | MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE) + | MCFSDRAMC_DACR_CASL(1) + | MCFSDRAMC_DACR_CBM(3) + | MCFSDRAMC_DACR_PS_32); + + /* Initialize DMR0 */ + MCFSDRAMC_DMR0 = (0 + | ((dramsize - 1) & 0xFFFC0000) + | MCFSDRAMC_DMR_V); + + /* Set IP (bit 3) in DACR */ + MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP; + + /* Wait 30ns to allow banks to precharge */ + for (i = 0; i < 5; i++) { + asm ("nop"); + } + + /* Write to this block to initiate precharge */ + *(u32 *)(CFG_SDRAM_BASE) = 0xA5A59696; + + /* Set RE (bit 15) in DACR */ + MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE; + + /* Wait for at least 8 auto refresh cycles to occur */ + for (i = 0; i < 2000; i++) { + asm(" nop"); + } + + /* Finish the configuration by issuing the IMRS. */ + MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS; + + /* Write to the SDRAM Mode Register */ + *(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xA5A59696; + } } |