diff options
| author | Jon Loeliger <jdl@freescale.com> | 2007-11-20 14:34:57 -0600 |
|---|---|---|
| committer | Jon Loeliger <jdl@freescale.com> | 2007-11-20 14:34:57 -0600 |
| commit | 890e9413c0af74a3d74f37d9ab6d19784990fa0c (patch) | |
| tree | 0e802d5d143e09751f85c76bf02f94aca023d077 /board/lwmon5 | |
| parent | 1d8a49eca1c7bdc8db1c47a92f9014a29ead03ae (diff) | |
| parent | 9a337ddc154a10a26f117fd147b009abcdeba75a (diff) | |
| download | u-boot-imx-890e9413c0af74a3d74f37d9ab6d19784990fa0c.zip u-boot-imx-890e9413c0af74a3d74f37d9ab6d19784990fa0c.tar.gz u-boot-imx-890e9413c0af74a3d74f37d9ab6d19784990fa0c.tar.bz2 | |
Merge commit 'remotes/wd/master'
Diffstat (limited to 'board/lwmon5')
| -rw-r--r-- | board/lwmon5/lwmon5.c | 26 |
1 files changed, 17 insertions, 9 deletions
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index 77f9989..9b24a7e 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -96,6 +96,23 @@ int board_early_init_f(void) gpio_write_bit(CFG_GPIO_FLASH_WP, 1); + /* + * Reset PHY's: + * The PHY's need a 2nd reset pulse, since the MDIO address is latched + * upon reset, and with the first reset upon powerup, the addresses are + * not latched reliable, since the IRQ line is multiplexed with an + * MDIO address. A 2nd reset at this time will make sure, that the + * correct address is latched. + */ + gpio_write_bit(CFG_GPIO_PHY0_RST, 1); + gpio_write_bit(CFG_GPIO_PHY1_RST, 1); + udelay(1000); + gpio_write_bit(CFG_GPIO_PHY0_RST, 0); + gpio_write_bit(CFG_GPIO_PHY1_RST, 0); + udelay(1000); + gpio_write_bit(CFG_GPIO_PHY0_RST, 1); + gpio_write_bit(CFG_GPIO_PHY1_RST, 1); + return 0; } @@ -231,15 +248,6 @@ int misc_init_r(void) out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE); /* - * Reset PHY's - */ - gpio_write_bit(CFG_GPIO_PHY0_RST, 0); - gpio_write_bit(CFG_GPIO_PHY1_RST, 0); - udelay(100); - gpio_write_bit(CFG_GPIO_PHY0_RST, 1); - gpio_write_bit(CFG_GPIO_PHY1_RST, 1); - - /* * Init display controller */ /* Setup dot clock (internal PLL, division rate 1/16) */ |