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| author | Peter Pearse <peter.pearse@arm.com> | 2008-01-07 15:34:22 +0000 |
|---|---|---|
| committer | Peter Pearse <peter.pearse@arm.com> | 2008-01-07 15:34:22 +0000 |
| commit | 4985ca5af3767ffe13ea96e1dc26f88c81084414 (patch) | |
| tree | 94db0464d5c7c643816dd3b4e823343496c2ed96 /board/lwmon5 | |
| parent | 2ae64f5135e51bb18753884d1265b99e89b5aedd (diff) | |
| parent | 5c740711f0ea5b51414b341b71597c4a0751be74 (diff) | |
| download | u-boot-imx-4985ca5af3767ffe13ea96e1dc26f88c81084414.zip u-boot-imx-4985ca5af3767ffe13ea96e1dc26f88c81084414.tar.gz u-boot-imx-4985ca5af3767ffe13ea96e1dc26f88c81084414.tar.bz2 | |
Merge with git://www.denx.de/git/u-boot.git
Diffstat (limited to 'board/lwmon5')
| -rw-r--r-- | board/lwmon5/lwmon5.c | 26 | ||||
| -rw-r--r-- | board/lwmon5/sdram.c | 2 | ||||
| -rw-r--r-- | board/lwmon5/sdram.h | 4 |
3 files changed, 20 insertions, 12 deletions
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index 77f9989..9b24a7e 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -96,6 +96,23 @@ int board_early_init_f(void) gpio_write_bit(CFG_GPIO_FLASH_WP, 1); + /* + * Reset PHY's: + * The PHY's need a 2nd reset pulse, since the MDIO address is latched + * upon reset, and with the first reset upon powerup, the addresses are + * not latched reliable, since the IRQ line is multiplexed with an + * MDIO address. A 2nd reset at this time will make sure, that the + * correct address is latched. + */ + gpio_write_bit(CFG_GPIO_PHY0_RST, 1); + gpio_write_bit(CFG_GPIO_PHY1_RST, 1); + udelay(1000); + gpio_write_bit(CFG_GPIO_PHY0_RST, 0); + gpio_write_bit(CFG_GPIO_PHY1_RST, 0); + udelay(1000); + gpio_write_bit(CFG_GPIO_PHY0_RST, 1); + gpio_write_bit(CFG_GPIO_PHY1_RST, 1); + return 0; } @@ -231,15 +248,6 @@ int misc_init_r(void) out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE); /* - * Reset PHY's - */ - gpio_write_bit(CFG_GPIO_PHY0_RST, 0); - gpio_write_bit(CFG_GPIO_PHY1_RST, 0); - udelay(100); - gpio_write_bit(CFG_GPIO_PHY0_RST, 1); - gpio_write_bit(CFG_GPIO_PHY1_RST, 1); - - /* * Init display controller */ /* Setup dot clock (internal PLL, division rate 1/16) */ diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index d4547e2..399da8a 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -71,7 +71,7 @@ static u32 is_ecc_enabled(void) void board_add_ram_info(int use_default) { - PPC440_SYS_INFO board_cfg; + PPC4xx_SYS_INFO board_cfg; u32 val; if (is_ecc_enabled()) diff --git a/board/lwmon5/sdram.h b/board/lwmon5/sdram.h index 7f847aa..6a7bf01 100644 --- a/board/lwmon5/sdram.h +++ b/board/lwmon5/sdram.h @@ -395,8 +395,8 @@ #define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) #define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) #define DDR0_26_TREF_MASK 0x00003FFF -#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) -#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF) +#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0) +#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF) #define DDR0_27 0x1B #define DDR0_27_EMRS_DATA_MASK 0x3FFF0000 |