Merge with git://www.denx.de/git/u-boot.git

2 files changed, 92 insertions, 35 deletions

diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c
index d916284..830ec19 100644
--- a/board/lwmon5/lwmon5.c
+++ b/board/lwmon5/lwmon5.c
@@ -45,16 +45,16 @@ int board_early_init_f(void)
 	mtdcr(uic0sr, 0xffffffff);  /* clear all. if write with 1 then the status is cleared  */
 	mtdcr(uic0er, 0x00000000);  /* disable all */
 	mtdcr(uic0cr, 0x00000000);  /* we have not critical interrupts at the moment */
-	mtdcr(uic0pr, 0xfffff7ff);  /* Adjustment of the polarity */
-	mtdcr(uic0tr, 0x00000810);  /* per ref-board manual */
+	mtdcr(uic0pr, 0xFFBFF1EF);  /* Adjustment of the polarity */
+	mtdcr(uic0tr, 0x00000900);  /* per ref-board manual */
 	mtdcr(uic0vr, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
 	mtdcr(uic0sr, 0xffffffff);  /* clear all */
 
 	mtdcr(uic1sr, 0xffffffff);  /* clear all */
 	mtdcr(uic1er, 0x00000000);  /* disable all */
 	mtdcr(uic1cr, 0x00000000);  /* all non-critical */
-	mtdcr(uic1pr, 0xFFFFC7AD);  /* Adjustment of the polarity */
-	mtdcr(uic1tr, 0x0600384A);  /* per ref-board manual */
+	mtdcr(uic1pr, 0xFFFFC6A5);  /* Adjustment of the polarity */
+	mtdcr(uic1tr, 0x60000040);  /* per ref-board manual */
 	mtdcr(uic1vr, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
 	mtdcr(uic1sr, 0xffffffff);  /* clear all */
 
@@ -62,9 +62,9 @@ int board_early_init_f(void)
 	mtdcr(uic2er, 0x00000000);  /* disable all */
 	mtdcr(uic2cr, 0x00000000);  /* all non-critical */
 	mtdcr(uic2pr, 0x27C00000);  /* Adjustment of the polarity */
-	mtdcr(uic2tr, 0xDFC00000);  /* per ref-board manual */
+	mtdcr(uic2tr, 0x3C000000);  /* per ref-board manual */
 	mtdcr(uic2vr, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
-	mtdcr(uic2sr, 0xffffffff);  /* clear all. Why this??? */
+	mtdcr(uic2sr, 0xffffffff);  /* clear all */
 
 	/* Trace Pins are disabled. SDR0_PFC0 Register */
 	mtsdr(SDR0_PFC0, 0x0);
@@ -158,13 +158,13 @@ int misc_init_r(void)
 	(void)flash_protect(FLAG_PROTECT_SET,
 			    -CFG_MONITOR_LEN,
 			    0xffffffff,
-			    &flash_info[0]);
+			    &flash_info[1]);
 
 	/* Env protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
 			    CFG_ENV_ADDR_REDUND,
 			    CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
-			    &flash_info[0]);
+			    &flash_info[1]);
 
 	/*
 	 * USB suff...
@@ -221,8 +221,8 @@ int misc_init_r(void)
 	udelay(500);
 	gpio_write_bit(CFG_GPIO_LIME_RST, 1);
 
-	/* Lime memory clock adjusted to 133MHz */
-	out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_133MHZ);
+	/* Lime memory clock adjusted to 100MHz */
+	out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_100MHZ);
 	/* Wait untill time expired. Because of requirements in lime manual */
 	udelay(300);
 	/* Write lime controller memory parameters */
@@ -237,6 +237,64 @@ int misc_init_r(void)
 	gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
 	gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
 
+	/*
+	 * Init display controller
+	 */
+	/* Setup dot clock (internal PLL, division rate 1/16) */
+	out_be32((void *)0xc1fd0100, 0x00000f00);
+
+	/* Lime L0 init (16 bpp, 640x480) */
+	out_be32((void *)0xc1fd0020, 0x801401df);
+	out_be32((void *)0xc1fd0024, 0x0);
+	out_be32((void *)0xc1fd0028, 0x0);
+	out_be32((void *)0xc1fd002c, 0x0);
+	out_be32((void *)0xc1fd0110, 0x0);
+	out_be32((void *)0xc1fd0114, 0x0);
+	out_be32((void *)0xc1fd0118, 0x01df0280);
+
+	/* Display timing init */
+	out_be32((void *)0xc1fd0004, 0x031f0000);
+	out_be32((void *)0xc1fd0008, 0x027f027f);
+	out_be32((void *)0xc1fd000c, 0x015f028f);
+	out_be32((void *)0xc1fd0010, 0x020c0000);
+	out_be32((void *)0xc1fd0014, 0x01df01ea);
+	out_be32((void *)0xc1fd0018, 0x0);
+	out_be32((void *)0xc1fd001c, 0x01e00280);
+
+#if 1
+	/*
+	 * Clear framebuffer using Lime's drawing engine
+	 * (draw blue rect. with white border around it)
+	 */
+	/* Setup mode and fbbase, xres, fg, bg */
+	out_be32((void *)0xc1ff0420, 0x8300);
+	out_be32((void *)0xc1ff0440, 0x0000);
+	out_be32((void *)0xc1ff0444, 0x0280);
+	out_be32((void *)0xc1ff0480, 0x7fff);
+	out_be32((void *)0xc1ff0484, 0x0000);
+	/* Reset clipping rectangle */
+	out_be32((void *)0xc1ff0454, 0x0000);
+	out_be32((void *)0xc1ff0458, 0x0280);
+	out_be32((void *)0xc1ff045c, 0x0000);
+	out_be32((void *)0xc1ff0460, 0x01e0);
+	/* Draw white rect. */
+	out_be32((void *)0xc1ff04a0, 0x09410000);
+	out_be32((void *)0xc1ff04a0, 0x00000000);
+	out_be32((void *)0xc1ff04a0, 0x01e00280);
+	udelay(2000);
+	/* Draw blue rect. */
+	out_be32((void *)0xc1ff0480, 0x001f);
+	out_be32((void *)0xc1ff04a0, 0x09410000);
+	out_be32((void *)0xc1ff04a0, 0x00010001);
+	out_be32((void *)0xc1ff04a0, 0x01de027e);
+#endif
+	/* Display enable, L0 layer */
+	out_be32((void *)0xc1fd0100, 0x80010f00);
+
+	/* TFT-LCD enable - PWM duty, lamp on */
+	out_be32((void *)0xc4000024, 0x64);
+	out_be32((void *)0xc4000020, 0x701);
+
 	return 0;
 }
 
@@ -463,3 +521,14 @@ void hw_watchdog_reset(void)
 	val = gpio_read_out_bit(CFG_GPIO_WATCHDOG) == 0 ? 1 : 0;
 	gpio_write_bit(CFG_GPIO_WATCHDOG, val);
 }
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+	return (ctrlc());
+}
+#endif
diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c
index 9a4a8ee..f906b85 100644
--- a/board/lwmon5/sdram.c
+++ b/board/lwmon5/sdram.c
@@ -54,7 +54,6 @@
 #define MY_TLB_WORD2_I_ENABLE	TLB_WORD2_I_ENABLE	/* disable caching on SDRAM */
 #endif
 
-void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
 void dcbz_area(u32 start_address, u32 num_bytes);
 void dflush(void);
 
@@ -474,7 +473,7 @@ static void program_ecc(u32 start_address,
 		blank_string(strlen(str));
 	} else {
 		/* ECC bit set method for cached memory */
-#if 1 /* test-only: will remove this define later, when ECC problems are solved! */
+#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
 		/*
 		 * Some boards (like lwmon5) need to preserve the memory
 		 * content upon ECC generation (for the log-buffer).
@@ -487,6 +486,11 @@ static void program_ecc(u32 start_address,
 
 		current_address = start_address;
 		while (current_address < end_address) {
+			/*
+			 * TODO: Th following sequence doesn't work correctly.
+			 * Just invalidating and flushing the cache doesn't
+			 * seem to trigger the re-write of the memory.
+			 */
 			ppcDcbi(current_address);
 			ppcDcbf(current_address);
 			current_address += CFG_CACHELINE_SIZE;
@@ -515,19 +519,6 @@ static void program_ecc(u32 start_address,
 }
 #endif
 
-static __inline__ u32 get_mcsr(void)
-{
-	u32 val;
-
-	asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
-	return val;
-}
-
-static __inline__ void set_mcsr(u32 val)
-{
-	asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
-}
-
 /*************************************************************************
  *
  * initdram -- 440EPx's DDR controller is a DENALI Core
@@ -535,8 +526,6 @@ static __inline__ void set_mcsr(u32 val)
  ************************************************************************/
 long int initdram (int board_type)
 {
-	u32 val;
-
 #if 0 /* test-only: will remove this define later, when ECC problems are solved! */
 	/* CL=3 */
 	mtsdram(DDR0_02, 0x00000000);
@@ -641,14 +630,6 @@ long int initdram (int board_type)
 	 * Perform data eye search if requested.
 	 */
 	denali_core_search_data_eye(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20);
-
-	/*
-	 * Clear possible errors resulting from data-eye-search.
-	 * If not done, then we could get an interrupt later on when
-	 * exceptions are enabled.
-	 */
-	val = get_mcsr();
-	set_mcsr(val);
 #endif
 
 #ifdef CONFIG_DDR_ECC
@@ -658,5 +639,12 @@ long int initdram (int board_type)
 	program_ecc(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
 #endif
 
+	/*
+	 * Clear possible errors resulting from data-eye-search.
+	 * If not done, then we could get an interrupt later on when
+	 * exceptions are enabled.
+	 */
+	set_mcsr(get_mcsr());
+
 	return (CFG_MBYTES_SDRAM << 20);
 }