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authorAnish Trivedi <anish@freescale.com>2010-11-09 10:21:30 -0600
committerAnish Trivedi <anish@freescale.com>2010-11-15 10:09:07 -0600
commit5992019f3fc6bddf9c2154d6d1a8c99759a24e4f (patch)
tree6ba8e54999df35f2230f1d9b825ed6f31e0c3091 /board/lwmon5/u-boot.lds
parent2cbb0e33bd31c9a34fcf3313329c005ae4ad44d6 (diff)
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ENGR00132909 MX53 Uboot: Support for TO2
Support new DDR script entitled "Rita_TO2_init_DDR2_CPU2_CMOS_TEST_CAL_v1.inc" for DDR2 boards including MX53 EVK, ARD, and ARM2 CPU2. These new settings did not apply to TO1. Therefore, changed the DCD for these boards to a plugin so that TO1 and TO2 can both be supported using conditional execution of new DDR settings. During bootup on TO2, DDR frequency is required to be below 400 MHz. Therefore, BOOT_CFG2[4] must be set to enable DDR at 333 MHz in ROM on all boards. Uboot determines silicon version and for TO2 boosts the VCC and VDDA voltages to 1.3V, after which the DDR frequency is also increased to 400 MHz. This requirement meant that uboot does not calibrate PLL2 anymore until the voltage is increased. Removed the calibration from lowlevel_init.S and from all mx53 include/configs files. Also required that during config_periph_clk(), only CBCMR register is touched to set source PLL. Other changes to CBCDR were removed. Switching to PLL2 bypass clk during reprogram was also removed. All these changes are required to increase DDR frequency to 400 MHz. DDR2 CPU2 board with TO1 requires the following hw cfgs: JP3 populated, and J8 set to 2-3. For DDR2 CPU2 board with TO2, both these jumpers should be depopulated. ARM2 CPU3 (with DDR3) DDR configurations were not changed. TO1 and TO2 can run well using existing DDR3 script. However, DCD was converted to plugin to align with other boards. Signed-off-by: Anish Trivedi <anish@freescale.com>
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