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| author | Stefan Roese <sr@denx.de> | 2010-11-26 15:45:48 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2010-12-17 09:43:45 +0100 |
| commit | a321148b5b38150b011a1df4ad198329a49e98a3 (patch) | |
| tree | 5a08d4444f86ef759c57edd0fd52b2a4b6565469 /board/lwmon5/sdram.c | |
| parent | f7b548adb56729f07cd5e96c10edc5260527d447 (diff) | |
| download | u-boot-imx-a321148b5b38150b011a1df4ad198329a49e98a3.zip u-boot-imx-a321148b5b38150b011a1df4ad198329a49e98a3.tar.gz u-boot-imx-a321148b5b38150b011a1df4ad198329a49e98a3.tar.bz2 | |
ppc4xx: Update lwmon5 board support
This patch includes the following changes for the lwmon5 board support:
- Enable cache in SDRAM
- Use common EHCI driver instead of the PPC4xx specific OHCI driver
This can be done since only high-speed devices are connected.
- Remove cached TLB entry again after ECC setup
- Use correct define for cache enabling
(CONFIG_4xx_DCACHE instead of CONFIG_SYS_ENABLE_SDRAM_CACHE)
- Enable FIT image support
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/lwmon5/sdram.c')
| -rw-r--r-- | board/lwmon5/sdram.c | 22 |
1 files changed, 18 insertions, 4 deletions
diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index f90efeb..b64b35a 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -45,10 +45,10 @@ * memory. * * If at some time this restriction doesn't apply anymore, just define - * CONFIG_SYS_ENABLE_SDRAM_CACHE in the board config file and this code should setup + * CONFIG_4xx_DCACHE in the board config file and this code should setup * everything correctly. */ -#ifdef CONFIG_SYS_ENABLE_SDRAM_CACHE +#ifdef CONFIG_4xx_DCACHE #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ #else #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ @@ -220,18 +220,32 @@ phys_size_t initdram (int board_type) program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20, MY_TLB_WORD2_I_ENABLE); +#if defined(CONFIG_DDR_ECC) +#if defined(CONFIG_4xx_DCACHE) + /* + * If ECC is enabled, initialize the parity bits. + */ + program_ecc(0, CONFIG_SYS_MBYTES_SDRAM << 20, 0); +#else /* CONFIG_4xx_DCACHE */ /* * Setup 2nd TLB with same physical address but different virtual address * with cache enabled. This is done for fast ECC generation. */ program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0); -#ifdef CONFIG_DDR_ECC /* * If ECC is enabled, initialize the parity bits. */ program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0); -#endif + + /* + * Now after initialization (auto-calibration and ECC generation) + * remove the TLB entries with caches enabled and program again with + * desired cache functionality + */ + remove_tlb(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20); +#endif /* CONFIG_4xx_DCACHE */ +#endif /* CONFIG_DDR_ECC */ /* * Clear possible errors resulting from data-eye-search. |