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| author | Grant Likely <grant.likely@secretlab.ca> | 2007-11-16 21:01:19 -0700 |
|---|---|---|
| committer | Grant Likely <grant.likely@secretlab.ca> | 2007-11-16 21:01:19 -0700 |
| commit | efe33035acd5f7c13963a4d52e5aac1b68612ae4 (patch) | |
| tree | 37d6ccca1c82953ae4c41451cb3ec5fe53e2dc3c /board/lwmon5/lwmon5.c | |
| parent | 4d4faae65e115e327425cd514c1a35146a85166b (diff) | |
| parent | 5947f6999aafa7c54c1390983d264a8463dfea8e (diff) | |
| download | u-boot-imx-efe33035acd5f7c13963a4d52e5aac1b68612ae4.zip u-boot-imx-efe33035acd5f7c13963a4d52e5aac1b68612ae4.tar.gz u-boot-imx-efe33035acd5f7c13963a4d52e5aac1b68612ae4.tar.bz2 | |
Merge branch 'origin' into kconfig-for-1.3.1
Conflicts:
drivers/Makefile
Diffstat (limited to 'board/lwmon5/lwmon5.c')
| -rw-r--r-- | board/lwmon5/lwmon5.c | 26 |
1 files changed, 17 insertions, 9 deletions
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index 77f9989..9b24a7e 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -96,6 +96,23 @@ int board_early_init_f(void) gpio_write_bit(CFG_GPIO_FLASH_WP, 1); + /* + * Reset PHY's: + * The PHY's need a 2nd reset pulse, since the MDIO address is latched + * upon reset, and with the first reset upon powerup, the addresses are + * not latched reliable, since the IRQ line is multiplexed with an + * MDIO address. A 2nd reset at this time will make sure, that the + * correct address is latched. + */ + gpio_write_bit(CFG_GPIO_PHY0_RST, 1); + gpio_write_bit(CFG_GPIO_PHY1_RST, 1); + udelay(1000); + gpio_write_bit(CFG_GPIO_PHY0_RST, 0); + gpio_write_bit(CFG_GPIO_PHY1_RST, 0); + udelay(1000); + gpio_write_bit(CFG_GPIO_PHY0_RST, 1); + gpio_write_bit(CFG_GPIO_PHY1_RST, 1); + return 0; } @@ -231,15 +248,6 @@ int misc_init_r(void) out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE); /* - * Reset PHY's - */ - gpio_write_bit(CFG_GPIO_PHY0_RST, 0); - gpio_write_bit(CFG_GPIO_PHY1_RST, 0); - udelay(100); - gpio_write_bit(CFG_GPIO_PHY0_RST, 1); - gpio_write_bit(CFG_GPIO_PHY1_RST, 1); - - /* * Init display controller */ /* Setup dot clock (internal PLL, division rate 1/16) */ |