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| author | Markus Klotzbuecher <mk@denx.de> | 2008-01-09 13:57:10 +0100 |
|---|---|---|
| committer | Markus Klotzbuecher <mk@denx.de> | 2008-01-09 13:57:10 +0100 |
| commit | 6a40ef62c4300e9f606deef0a4618cbc4b514a51 (patch) | |
| tree | c01bdd0e773d092f13af05567fa92fb9072df9e0 /board/lwmon5/lwmon5.c | |
| parent | 245a362ad3c0c1b84fccc9fec7b623eb14f6e502 (diff) | |
| parent | 07eb02687f008721974a2fb54cd7fdc28033ab3c (diff) | |
| download | u-boot-imx-6a40ef62c4300e9f606deef0a4618cbc4b514a51.zip u-boot-imx-6a40ef62c4300e9f606deef0a4618cbc4b514a51.tar.gz u-boot-imx-6a40ef62c4300e9f606deef0a4618cbc4b514a51.tar.bz2 | |
Merge git://www.denx.de/git/u-boot
Conflicts:
board/tqm5200/tqm5200.c
Diffstat (limited to 'board/lwmon5/lwmon5.c')
| -rw-r--r-- | board/lwmon5/lwmon5.c | 26 |
1 files changed, 17 insertions, 9 deletions
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index 77f9989..9b24a7e 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -96,6 +96,23 @@ int board_early_init_f(void) gpio_write_bit(CFG_GPIO_FLASH_WP, 1); + /* + * Reset PHY's: + * The PHY's need a 2nd reset pulse, since the MDIO address is latched + * upon reset, and with the first reset upon powerup, the addresses are + * not latched reliable, since the IRQ line is multiplexed with an + * MDIO address. A 2nd reset at this time will make sure, that the + * correct address is latched. + */ + gpio_write_bit(CFG_GPIO_PHY0_RST, 1); + gpio_write_bit(CFG_GPIO_PHY1_RST, 1); + udelay(1000); + gpio_write_bit(CFG_GPIO_PHY0_RST, 0); + gpio_write_bit(CFG_GPIO_PHY1_RST, 0); + udelay(1000); + gpio_write_bit(CFG_GPIO_PHY0_RST, 1); + gpio_write_bit(CFG_GPIO_PHY1_RST, 1); + return 0; } @@ -231,15 +248,6 @@ int misc_init_r(void) out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE); /* - * Reset PHY's - */ - gpio_write_bit(CFG_GPIO_PHY0_RST, 0); - gpio_write_bit(CFG_GPIO_PHY1_RST, 0); - udelay(100); - gpio_write_bit(CFG_GPIO_PHY0_RST, 1); - gpio_write_bit(CFG_GPIO_PHY1_RST, 1); - - /* * Init display controller */ /* Setup dot clock (internal PLL, division rate 1/16) */ |